JP2011151404A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of reducing a chip area or increasing the speed of sense operation by reducing the difference between delay times of outputs from a regular cell (16) and a reference cell (26) to a sense amplifier (30). <P>SOLUTION: The semiconductor device includes: regular cells (16) which are disposed in a regular sector (10) and are connected to word lines (14); a plurality of reference cells (26) which are used when data is read out from the regular sector (10); a reference word cell (24) to which the plurality of reference cells are connected; and a dummy word line (25) disposed adjacent to the reference word line. One of the plurality of reference cells (26) is selected in accordance with a word line distance of the regular cell (16) from which data is read out. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor memory device.

  Some semiconductor memory devices compare the data in the reference cell and the regular cell and read the data from the regular cell. A flash memory will be described as an example with reference to FIG.

  FIG. 1 is a block diagram around a memory cell of a conventional flash memory. A regular cell 16 is arranged in the regular sector 10. Word lines 14a, 14b and 14c connected to the word driver 12 and a bit line 18 connected to the sense amplifier 30 are connected to the regular cells 16a, 16b and 16c in the regular cells. The reference cell 26 is arranged in the reference sector 20. The reference cell 26 is connected to a word line 24 connected to the reference word driver 22 and a connection line 32 connected to the sense amplifier 30.

  Data reading will be described by taking the regular cell 16a as an example. For example, the word line 14a connected to the regular cell 16a is selected by the word driver 12. The bit line 18 connected to the regular cell 16a is selected. The sense amplifier 30 compares the threshold voltages of the regular cell 16a and the reference cell 26. As a result, the regular cell 16a is read as “0” or “1”.

  In the present specification and claims, the distance of the word line 14 from the word driver 12 to each regular cell 16 is defined as the word line distance of the regular cell 16. Further, the distance of the reference word line from the reference word driver 22 to each reference cell 26 is the reference word line distance of the reference cell 26.

  As a semiconductor memory device in which a plurality of reference cells are arranged, Patent Document 1 discloses a semiconductor device in which a plurality of reference cells having different resistances and capacities up to a sense amplifier are arranged. Patent Document 2 discloses a semiconductor device in which a reference cell is arranged near a regular cell.

Japanese Patent Laid-Open No. 9-270195 Japanese Patent Laid-Open No. 10-11985

  In the prior art, the word driver 12 is arranged on one side of the regular sector 10 for chip area reduction. Further, the number of regular cells 16 connected to one of the word lines 14 is increased to reduce the chip area. In this way, the length of the word line 14 becomes long when trying to achieve the chip area reduction. As a result, the following problems occur.

  In FIG. 1, when the length of the word line 14 described using the regular cells 16a, 16b and 16c having different word line distances La, Lb and Lc is increased, the difference between the word line distances La, Lb and Lc is increased. As a result, the difference in resistance and capacitance of the word line 14 added to the regular cell 16 also increases. As a result, delay times of outputs from the regular cells 16a, 16b and 16c to the sense amplifier 30 are different.

  For example, consider the case where the delay time of the output from the reference cell 26 to the sense amplifier 30 is set to be substantially the same as that of the regular cell 16b. In this case, the delay time of the output of the regular cell 16 a to the sense amplifier 30 is earlier than that of the reference cell 26. On the other hand, the delay time of the output of the regular cell 16 c to the sense amplifier 30 is later than that of the reference cell 26. As described above, when the delay time is different for each regular cell 16, there is no operation margin of the sense amplifier 30 and the operation becomes unstable. In order to prevent this, the number of regular cells connected to the word line 14 is limited. Alternatively, it is necessary to increase the operation time of the sense amplifier 30. That is, it is difficult to achieve both a reduction in chip area and a high speed sensing operation.

  It is an object of the present invention to provide a semiconductor device capable of reducing the difference in delay time between the output of a regular cell and a reference cell to a sense amplifier and reducing the chip area or speeding up the sensing operation.

  The present invention provides a regular cell disposed in a regular sector and connected to a word line, a reference cell used when reading data from the regular cell, a reference word line connected to the reference cell, and the reference word And a dummy word line disposed beside the line. According to the present invention, by providing a dummy word line beside the reference word line, a capacity corresponding to the capacity between adjacent word lines in the regular sector can be provided between the dummy word line and the reference word line. it can. As a result, the capacity added to the reference word line becomes close to the capacity of the word line. Thereby, the difference in the delay time of the output to the sense amplifier of a regular cell and a reference cell can be made small. Therefore, a semiconductor device capable of reducing the chip area or speeding up the sensing operation can be provided.

  The present invention can be a semiconductor device in which the dummy word line is connected to a fixed power source. According to the present invention, the capacity added to the reference word line can be made closer to the capacity of the word line.

  The present invention may be a semiconductor device in which an interval between the reference word line and the dummy word line is substantially the same as an interval between adjacent word lines in the regular sector. According to the present invention, the capacity added to the reference word line can be made closer to the capacity of the word line.

  The present invention may be a semiconductor device that includes a plurality of the reference cells and selects one of the plurality of reference cells according to the word line distance of the regular cell from which data is read. According to the present invention, by selecting one of a plurality of reference cells according to the word line distance of a regular cell from which data is read, the difference in delay time between the output of the regular cell and the reference cell to the sense amplifier is reduced. Can be small.

  According to the present invention, the reference cells can be semiconductor devices having different reference word line distances. According to the present invention, it is possible to select a reference cell having a reference word line distance corresponding to the word line distance. Thereby, the difference of the delay time of the output to the sense amplifier of a regular cell and a reference cell can be made smaller.

  The present invention can be a semiconductor device including a sense amplifier connected to the regular cell from which data is read and the selected reference cell. According to the present invention, by connecting the regular cell from which data is read and the corresponding reference cell to the sense amplifier, the difference in the delay time of the output from the regular cell to the sense amplifier can be reduced.

  The present invention may be a semiconductor device that includes a plurality of sub-sectors of the regular cell, and the sense amplifier connected to the regular cell in each sub-sector is connected to the same reference cell. Furthermore, the present invention can be a semiconductor device including a selection circuit that selects the reference cell according to the distance of the word line and connects to the sense amplifier. According to the present invention, the regular cell from which data is read and the corresponding reference cell can be reliably connected to the sense amplifier.

  The present invention may be a semiconductor device in which the reference word driver is disposed adjacent to the word driver. According to the present invention, both the reference word driver and the word driver can be arranged near the booster circuit. Thereby, the output to a regular cell and a reference cell can be performed at substantially the same timing. Therefore, the difference in output delay time between the regular cell and the reference cell to the sense amplifier can be reduced.

  In the present invention, the regular cell may be a cell that stores a plurality of bits, and each reference cell may be a semiconductor device having a plurality of sub-reference cells. According to the present invention, it is possible to reduce the chip area or speed up the sensing operation in a semiconductor device having a cell that stores a plurality of bits that are required to read data with a subtle threshold voltage difference between the cells. It can be.

  According to the present invention, the sub-reference cells belonging to the same reference cell can be semiconductor devices connected to the same reference word line. In the present invention, the plurality of sub-reference cells belonging to the same reference cell may be a semiconductor device connected to the different reference word lines. According to the present invention, output delay times from the plurality of sub-reference cells belonging to the same reference cell to the sense amplifier can be made substantially the same.

  The present invention may be a semiconductor device in which the regular cell is a flash memory cell. According to the present invention, it is possible to reduce the chip area or speed up the sensing operation in a flash memory having a large output delay due to the word line distance.

  According to the present invention, it is possible to provide a semiconductor device capable of reducing the difference in delay time between the output of the regular cell and the reference cell to the sense amplifier and reducing the chip area or speeding up the sensing operation.

FIG. 1 is a block diagram around a regular sector of a conventional flash memory. FIG. 2 is a block diagram of the flash memory according to the first embodiment. FIG. 2A is a diagram around the regular sector, and FIG. 2B is a diagram around the reference sector. FIG. 3 is a cross-sectional view in the width direction of the word lines of the transistors constituting the regular cell and reference cell of the flash memory. FIG. 4 is a block diagram of the periphery of the regular sector for explaining a reference cell selection method of the flash memory according to the first embodiment. FIG. 5 is a block diagram around a regular sector of a flash memory according to a modification of the first embodiment, and is a diagram for explaining a method of selecting a reference cell. FIG. 6 is a block diagram around the regular sector of the flash memory according to the second embodiment. FIG. 7 is a diagram illustrating a selection circuit and a reference sector of the flash memory according to the second embodiment. FIG. 8 is a diagram for explaining a reference sector of the flash memory according to the second embodiment. FIG. 9 is a diagram of the vicinity of a reference sector and a selection circuit of a flash memory according to a modification of the second embodiment. FIG. 10 is a diagram of the reference sector of the flash memory according to the third embodiment. FIG. 11 is a diagram illustrating an arrangement of each block of the flash memory according to the fourth embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 2A is a block diagram around the regular sector of the flash memory according to the first embodiment, and FIG. 2B is a diagram of the reference sector. The regular sector 10 is divided into sub-sectors 11a, 11b and 11c. Regular cells 16a, 16b and 16c in regular sector 10 are arranged in sub-sectors 11a, 11b and 11c, respectively. The regular cells 16a, 16b and 16c are connected to word lines 14a, 14b and 14c connected to the word driver 12, respectively, and are connected to bit lines 18a, 18b and 18c connected to the sense amplifier 30, respectively. .

  The word driver 12 has a function of driving a word line 14 connected to a regular cell 16 for writing / erasing / reading data. The sense amplifier 30 selects the bit line 18 connected to the regular cell 16 for writing / erasing / reading. Further, the regular cell 16 to be read is compared with the reference cell 26 to read data.

  Reference cells 26 a, 26 b and 26 c used when reading data from the regular cell 16 are arranged in the reference sector 20. The reference word line 24 is connected to the reference word driver 22 and has a rectangular wave shape. Reference cells 26a, 26b and 26c are connected to the same reference word run 24. Each reference cell 26a, 26b and 26c has a different reference word line distance.

  Each reference cell 26a, 26b and 26c is connected to a connection line 32a, 32b and 32c connected to the sense amplifier 30, respectively. More specifically, as shown in FIG. 2B, S and D1, which are connection regions 28, are connected to the reference cell 26a via the contact portion 29. These are connected to a source region and a drain region of a transistor constituting a reference cell 26a described later. That is, the connection line 32a is connected to the reference cell 26a via S and D1. The same applies to the reference cells 26b and 26c.

  FIG. 3 is a cross-sectional view in the width direction of the word lines of the transistors constituting the regular cell 16 and the reference cell 26 of the flash memory. An N-type drain region 52 and a source region 53 are formed in a P-type silicon semiconductor substrate 50 (or a P-type region in the semiconductor substrate). A tunnel oxide film 54 (silicon oxide film) is formed on the semiconductor substrate 50. A floating gate 55 is formed on the tunnel oxide film 54 as a charge storage layer. An insulating film 58 is formed on the floating gate 55, and a word line 56 also serving as a control gate is formed thereon. This transistor functions as a nonvolatile memory cell by accumulating charges in the floating gate 55 as a charge accumulation layer.

  In writing data into the regular cell 16, a positive voltage is applied to the word line 56 and the drain region 52, respectively, and a current is passed through the regular cell 16. Hot electrons (high energy electrons) are generated by the voltage applied at this time. The hot electrons are injected into the floating gate 55 of the charge storage layer. Further, the threshold voltage of the transistor can be adjusted by adjusting the voltage to be applied. To erase data in the regular cell 16, a negative voltage is applied to the word line 56 and a positive voltage is applied to the semiconductor substrate 50. Thus, the electrons injected into the floating gate 55 of the charge storage layer are extracted from the semiconductor substrate 50. Thereby, the threshold voltage of the transistor can be reduced.

  Data is read by applying a predetermined voltage to the word line 56, grounding the source region 53, and applying a positive voltage to the drain region 52. The current flowing between the source region 53 and the drain region 52 of the transistor varies depending on the threshold voltage. Therefore, the sense amplifier 30 compares this current with the current of the reference cell 26 to determine “0” or “1” of the data. As a result, data is read out.

  Then, one of the reference cells 26 is selected according to the word line distance of the regular cell 16 from which data is read. For example, when reading data from the regular cell 16a having a short word line distance La, the reference cell 26a having a short reference word line distance is selected. Then, the regular cell 16a and the reference cell 16a are connected to the sense amplifier 30. Similarly, when reading data from the regular cells 16b and 16c, the reference cells 26b and 26c are selected and connected to the sense amplifiers 30b and 30c, respectively.

  At this time, the reference word line distance of the reference cell 26a is such that, for example, the delay time of the output from the reference cell 26a to the sense amplifier 30 is the average delay time of the output to the sense amplifier 30 of the regular cell 16a in the sub-sector 11a. It can be determined to be. As described above, the selection of the reference cell 26 a according to the word line distance of the regular cell 16 can be selected according to the delay time of the output from the regular cell 16 and the reference cell 26 to the sense amplifier 30.

  Further, since the output delay time from the reference cell 26a to the sense amplifier 30 is the average delay time for the output to the sense amplifier 30a of the regular cell 16a in the sub-sector 11a, for example, the reference word line distance of the reference cell 26a. Can be determined to be the average word line distance of the regular cells 16 in the subsector 11a.

  The reference word line distances of the reference cells 26b and 26c can be similarly determined.

  As described above, one of the reference cells 26 having different reference word line distances is selected in accordance with the word line distance of the regular cell 16 from which data is read, and the regular cell 16 from which data is read and the selected reference cell 26 are selected. Are connected to the sense amplifier 30. Thereby, the difference in the delay time of the output to the sense amplifier 30 of the regular cell 16 and the reference cell 26 can be made small. For this reason, the operation margin of the sense amplifier 30 can be ensured. Thus, a semiconductor device capable of reducing the chip area or speeding up the sensing operation can be provided.

  Next, a method for connecting the reference cell 26 will be described. FIG. 4 is a block diagram around the regular sector for explaining a method of connecting the reference cells 26 according to the first embodiment. Details in the word line 14, the regular cell 16, the reference word driver 22, and the reference sector 20 are the same as those in FIG. The regular sector 10 is divided into sub-sectors 11a, 11b and 11c. Regular cells 16a, 16b and 16c (not shown) in subsectors 11a, 11b and 11c are connected to sense amplifiers 30a, 30b and 30c via bit lines 18a, 18b and 18c, respectively. The sense amplifiers 30a, 30b, and 30c are connected to the reference cells 26a, 26b, and 26c via connection lines 32a, 32b, and 32c, respectively.

  As described above, a plurality of sub-sectors 11a, 11b, and 11c obtained by dividing the regular sector 10 according to the word line distance of the regular cell 16 are provided. The sense amplifiers 30a, 30b and 30c connected to the regular cells 16 in the sub-sectors 11a, 11b and 11c are physically connected to the same reference cells 26a, 26b and 26c, respectively, using connection lines 32a, 32b and 32c. ing. In this way, the regular cell 16 from which data is read and the selected reference cell 26 can be reliably connected to the sense amplifier 30a.

  Next, a flash memory having a different connection method for the reference cells 26 will be described as a modification of the first embodiment. FIG. 5 is a block diagram of the periphery of the regular sector for explaining a method of connecting the reference cells 26 of the flash memory according to the modification of the first embodiment. The configurations of the word driver 12, the word line 14, the regular cell 16, the reference word driver 22, and the reference word line 24 are the same as those in the first embodiment and are not described.

  The regular sector 10 is divided by the output of the bit length. In FIG. 5, it is divided into I / O0 to I / O15 every 16 bits. A selection circuit 34 for selecting the reference cell 26 is provided between the sense amplifier 30 and the reference cells 26a, 26b, 26c and 26d. A column selection signal 36 is input to the sense amplifier 30 and the selection circuit 34.

  When data is read from the regular cells 16 in the I / O0, I / O8, I / O1, and I / O9 with short word line distances, the column selection signal 36 is input to the sense amplifier 30, and these I / O Select a regular cell. The column selection signal 36 is also input to the selection circuit 34, selects the reference cell 26a having a short reference word line distance, and connects it to the sense amplifier 30. When reading the cells in the other I / O, the reference cell 26 corresponding to the word line distance of the regular cell 16 in the regular sector 10 is selected and connected to the sense amplifier 30. Can do. As described above, the selection circuit 34 has a function of selecting one of the reference cells 26 according to the word line distance of the regular cell 16 and connecting it to the sense amplifier 30.

  Also in the modification of the first embodiment, the regular cell 16 from which data is read and the selected reference cell 26 can be reliably connected to the sense amplifier 30a.

  The modification of the first embodiment does not require a plurality of connection lines 32 as in the first embodiment, but the selection circuit 34 is necessary. Therefore, it is possible to determine which of the first embodiment and the modification is applied in consideration of the chip areas of the plurality of connection lines 32 and the selection circuit 34.

  The first embodiment and the modification are examples in which there are three reference cells 26 and four reference cells 26, respectively. However, if there are a plurality of reference cells 26, the same effect can be obtained. If the number of reference cells 26 is large, the difference in delay time between the regular cell 16 and the output of the reference cell 26 to the sense amplifier 30 can be made smaller. However, the areas of the reference sector 20 and the selection circuit 30 are increased. The number of reference cells 26 is determined in consideration of these.

  The second embodiment is an example of a flash memory in which the regular cell 16 is a cell that stores multiple values (four values), that is, a plurality (two bits). The transistors constituting the regular cell 16 and the reference cell 26 are the same as those in the first embodiment. In FIG. 3, 2 bits can be stored by dividing the amount of charge accumulated in the floating gate 45 for accumulating charges into four. It is possible to store the four values (00), (01), (10) and (11) in one cell, assuming that the accumulation state of electric charges in each bit is “0” and the state in which no charge is accumulated is “1”. it can.

  FIG. 6 is a block diagram of the periphery of the memory cell of the flash memory according to the second embodiment. The configurations of the word driver 12, the word line 14, the regular cell 16, the reference word driver 22, and the reference word line 24 are the same as those in the first embodiment and are not described. Further, as in the modification of the first embodiment, the regular sector 10 is divided into I / O0 to I / O15 by the output of the bit length. For example, when reading data from the regular cells 16 in the I / O 0, I / O 8, I / O 1, and I / O 9 with short word line distances, the selection circuit 34 uses the column selection signal 36 to read the data in the I / O. The regular cell 16 and the reference cell 26 a are selected and connected to the sense amplifier 30. In addition, a selection switching circuit 38, a counter 40, a buffer 42, and an output circuit 44 are provided. As described above, the selection of one of the reference cells 26 by the word line distance of the regular cell 16 from which the selection circuit 34 reads data by the column selection signal 36 is the same as in the modification of the first embodiment.

  FIG. 7 is a diagram showing the selection circuit 34 and the reference cell 26. The reference word driver 22 and the reference word line 24 are not shown. A reference cell RS1 (26a) corresponding to a regular cell having a short word line distance has a plurality of sub-reference cells S1 (27a), S2 (27b) and S3 (27c). Similarly, the reference cells RS2 (26b), RS3 (26c), and RS4 (26d) have a plurality of sub-reference cells S1, S2, and S3. Each of the sub-reference cells S1 (27a), S2 (27b), and S3 (27c) is connected to the selection circuit 34. The selection circuit 34 selects any one of the sub-reference cells S1, S2, and S3 included in the reference cells RS1, RS2, RS3, and RS4 and connects it to the sense amplifier 30.

  FIG. 8 is a diagram for explaining the reference sector 20. The reference cells RS3 (26c) and RS4 (26d) are omitted. The reference word line 24 connected to the reference word driver 22 has a rectangular wave shape, and is connected to the reference cells RS1 (26a) and RS2 (26b). A plurality of sub-reference cells S1 (27a), S2 (27b), and S3 (27c) included in the same reference cell RS1 (26a) are arranged adjacent to each other and connected to the same reference word line 24. Since they are arranged adjacent to each other, they have approximately the same reference word line distance.

  Connection regions D1a (28a) and S (28s) are connected to the drain region and the source region of the sub-reference cell S1 (27a) through contact portions 29a and 29s. Similarly, D1b (28b) and S (28s) are connected to the sub-reference cell S2 (27b) via the contact portions 29b and 29s, and D1c (28c) and S (28s) are connected to the sub-reference cell 27c via the contact portions 29c and 29s. ) Are connected.

  The same applies to the sub-reference cells S1 (27a), S2 (27b), and S3 (27c) included in the reference cell RS2 (26b). The reference cell 26b has a longer reference word line distance than the reference cell 26a.

  Next, a method of reading multi-value data from the regular cell 16 in the regular sector 10 will be described. Three sub-reference cells S1, S2 and S3 are used to read out the four values. First, the sub-reference cell S2 is used to determine whether the regular cell 16 is “0” or “1”. Next, when the regular cell 16 is “0”, S1 is used to determine (00) and (01). When the regular cell 16 is “1”, S3 is used to determine (10) and (11).

  A specific sub-reference cell selection method will be described below. First, when an address is specified and reading is started, the selection circuit 34 selects the reference cell 26 according to the word line distance of the regular cell 16 from which data in the regular sector 10 is read by the column selection signal 36. For example, it is assumed that the reference cell RS1 (26a) is selected. At this time, “1” is input to the counter 40 and “1” is input to the buffer 42.

  Next, when both the output of the counter 40 and the output of the buffer 42 are “1”, the sub-reference cell S2 (27b) of the reference cells RS1 (26a) is selected from the signal of the selection switching circuit 38. Regular cell 16 and S2 (27b) are connected to sense amplifier 30, and sense amplifier 30 determines whether the left bit is "0" or "1". When outputting the result from the sense amplifier 30, “2” is input to the counter 40 and the output of the sense amplifier 30 is input to the buffer 42.

  Next, reading is performed again. At this time, if the counter 40 is “2” and the buffer 42 is “0”, the selection switching circuit 38 causes the selection circuit 34 to select S1 (27a). On the other hand, when the counter 40 is “2” and the buffer 38 is “1”, the selection switching circuit 38 causes the selection circuit 34 to select S3 (27c). The regular cell 16 and S1 (27a) or S3 (27c) are connected to the sense amplifier 30, and the sense amplifier 30 determines whether the right bit is “0” or “1”.

  At the time of the second output from the sense amplifier 30 (the output “2” of the counter 40), the output circuit 44 is either (00), (01), (10) or (10) depending on the outputs of the buffer 42 and the sense amplifier 30. 11) is output.

  As in the second embodiment, in the regular cell 16 that stores multiple values, a plurality of sub-reference cells 27 are required. For example, in the case of a quaternary cell, three sub-reference cells 27 are required. As described above, the plurality of sub-reference cells (27) S1, S2, and S3 included in the same reference cell 26 have approximately the same reference word line distance. As a result, the outputs of these sub-reference cells 27 to the sense amplifier 30 have substantially the same delay time.

  The almost same delay time means that the difference in delay time is sufficiently small with respect to the distribution of the delay time of the output from the regular cell 16 to the sense amplifier 30 using the same reference cell 26. Thereby, when considering the operation margin of the sense amplifier 30, it is not necessary to consider the difference in the delay time of the output from the sub-reference cell 27 that the same reference cell 26 has. Therefore, an operation margin for the sense operation can be ensured.

  Then, by selecting the reference cell 26 corresponding to the word line distance of the regular cell 16, the output delay time from the sub-reference cell 27 in the reference cell 26 to the sense amplifier 30 and the regular cell 16 to the sense amplifier 30 are selected. The difference in output delay time can be reduced. Thus, a semiconductor device capable of reducing the chip area or speeding up the sensing operation can be provided.

  A flash memory having a regular cell 16 that stores a plurality of bits in the regular sector 10 is required to read data by a subtle difference in threshold voltage of the regular cell 16. Therefore, if the difference in delay time between the regular cell 16 and the reference cell 26 output to the sense amplifier 30 is large, the operation of the sense amplifier 30 becomes more unstable. Therefore, it is an obstacle to further miniaturization and higher speed. Therefore, by applying the present invention, the effect can be exhibited more.

  FIG. 9 is a view of the vicinity of the reference sector 20 and the selection circuit 34 of the flash memory according to a modification of the second embodiment. The configuration other than the reference sector 20 is the same as that of the second embodiment. Reference sectors 20a, 20b and 20c are arranged. In the reference sector 20a, sub-reference cells S1 of reference cells RS1, RS2, RS3, and RS4 are arranged.

  Each sub-reference cell S1 in the reference sector 20a is connected to the same reference word line 24a. Similarly, sub-reference cells S2 and S3 are arranged in the reference sectors 20b and 20c, respectively, and are connected to different reference word lines (reference word lines are not shown).

  The plurality of sub-reference cells S1, S2, and S3 included in the same reference cell RS1 are arranged to have substantially the same reference word line distance. Similarly, S1, S2, and S3 of RS2, RS3, and RS4 are arranged so as to have substantially the same reference word line distance.

  As in the modification, the plurality of sub-reference cells 27 of the same reference cell 16 may be arranged in different reference sectors 20 and connected to different reference word lines 24. In this case, the same effect as that of the second embodiment can be obtained. The second embodiment and the modification are examples in the case of four values as multivalues, but may be other than four values.

  The third embodiment is an example in which a dummy word line 25 is provided in the reference sector 20. FIG. 10 is a diagram of the reference sector of the flash memory according to the third embodiment. The configuration other than the provision of the dummy word line 25 is the same as that in FIG. 2B of the first embodiment. Although not shown, the word line driver 12 and the regular cell 10 disposed in the regular sector 10 and connected to the word line 14 are provided as in the first embodiment. As shown in FIG. 10, the reference sector 20 has a rectangular-wave reference word line 24 connected to a reference cell 26. Further, a dummy word line 25 is provided beside the reference word line 24.

  As the memory cell becomes finer, the interval between the word lines 14 in the regular sector 10 becomes narrower. In this case, the capacity with the adjacent word line 14 is increased, which affects the delay time of the output from the regular cell 16 to the sense amplifier 30. However, only the own resistance and capacitance are added to the reference word line 24 according to the first embodiment. For this reason, even if the word line distance of the regular cell 16 connected to the sense amplifier 30 and the reference word line distance of the reference cell 26 are approximately equal, the output delay of the regular cell 16 and the reference cell 26 to the sense amplifier is delayed. There will be a difference in time.

  Therefore, a dummy word line 25 is provided, and a capacity corresponding to the capacity between adjacent word lines 14 is provided between the dummy word line 25 and the reference word line 24. As a result, the capacity added to the reference word line 24 becomes close to the capacity of the word line 14. Thus, the difference in delay time between the regular cell 16 and the reference cell 26 output to the sense amplifier 30 can be reduced. Thus, a semiconductor device capable of reducing the chip area or speeding up the sensing operation can be provided.

  It is preferable to connect the dummy word line 25 to a fixed voltage. As a result, the capacity added to the reference word line 24 can be made closer to the capacity of the word line 14. Therefore, the difference in output delay time between the regular cell 16 and the reference cell 26 to the sense amplifier 30 can be further reduced.

  The interval L between the reference word line 24 and the dummy word line 25 is preferably substantially the same as the interval between adjacent word lines 14 in the sector. As a result, the capacity added to the reference word line 24 can be made substantially the same as the capacity between the word lines. Therefore, the difference in output delay time between the regular cell 16 and the reference cell 26 to the sense amplifier 30 can be further reduced.

  Providing the dummy word line 25 can be applied to the case where there is only one reference cell 25 in addition to the case where a plurality of reference cells 26 are arranged. Also in this case, the difference in delay time between the output of the regular cell 16 and the reference cell 26 to the sense amplifier 30 can be further reduced.

  The fourth embodiment is an example in which the reference sector 20 and the reference word driver 22 are adjacent to the word driver 12. FIG. 11 is a diagram illustrating the arrangement of the flash memory according to the fourth embodiment. A plurality of regular sectors 10 are arranged on both sides of the word driver 12, and a corresponding sense amplifier 30 is arranged below the plurality of regular sectors 10. The reference word driver 22 is adjacent to the word driver 12.

Thus, both the reference word driver and the word driver can be arranged near the booster circuit. Thereby, the output to a regular cell and a reference cell can be performed at substantially the same timing. Therefore, the difference in output delay time between the regular cell and the reference cell to the sense amplifier can be reduced.
Further, the reference word driver 22 is disposed adjacent to the sense amplifier 30 side of the word driver 12, and the reference sector 20 is disposed adjacent to the sense amplifier 30 and the reference word driver 22. As a result, the output from the reference cell in the reference sector 20 to the sense amplifier 30 is reduced little, and the sensing accuracy in the sense amplifier 30 can be improved.

  In the first to fourth embodiments, the flash memory has been described as an example. In the flash memory, the sense amplifier 30 performs sensing by comparing the currents of the regular cell 16 and the reference cell 26. Therefore, unlike Patent Document 1 using a differential sense amplifier, there is not much output delay due to resistance and capacitance from the sense amplifier 30 to the cell and reference cell, and output delay due to the word line distance is large. Therefore, as in the embodiment, by applying the present invention to the case where the regular cell 16 and the reference cell 26 are flash memory cells, the effect can be further exhibited.

  In addition to the flash memory, the effect can be further exerted by applying it to a semiconductor memory device that performs sensing by comparing the currents of the regular cell 16 and the reference cell 26.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

  10 regular sectors, 11, 11a, 11b, 11c sub-sectors, 12 word drivers, 14a, 14b, 14c, word lines, 16, 16a, 16b, 16c regular cells, 30 sense amplifiers, 18, 18a, 18b, 18c bit lines, 20 reference sectors, 26, 26a, 26b, 26c reference cells, 24 reference word lines, 25 dummy word lines, 30 sense amplifiers.

Claims (13)

A regular cell located in a regular sector and connected to a word line;
A reference cell for use in reading data from the regular cell;
A reference word line connected to the reference cell;
And a dummy word line provided beside the reference word line.   The semiconductor device according to claim 1, wherein the dummy word line is connected to a fixed power source. 3. The semiconductor device according to claim 1, wherein an interval between the reference word line and the dummy word line is substantially the same as an interval between adjacent word lines in the regular sector. Comprising a plurality of said reference cells;
4. The semiconductor device according to claim 1, wherein one of the plurality of regular cells is selected according to a word line distance of the regular cell from which data is read. 5.   The semiconductor device according to claim 4, wherein the reference cells have different reference word line distances.   5. The semiconductor device according to claim 4, further comprising a sense amplifier connected to the regular cell from which data is read and the selected reference cell. Comprising a plurality of sub-sectors of the regular cell;
The semiconductor device according to claim 6, wherein the sense amplifier connected to the regular cell in each sub-sector is connected to the same reference cell.   The semiconductor device according to claim 6, further comprising a selection circuit that selects the reference cell according to the distance of the word line and connects to the sense amplifier.   The reference word driver for driving the reference word line and the word driver for driving the word line, wherein the reference word driver is disposed adjacent to the word driver. The semiconductor device described.   6. The semiconductor device according to claim 5, wherein the regular cell is a cell that stores a plurality of bits, and each reference cell has a plurality of sub-reference cells.   The semiconductor device according to claim 10, wherein sub-reference cells included in the same reference cell are connected to the same reference word line.   The semiconductor device according to claim 10, wherein the plurality of sub-reference cells included in the same reference cell are connected to different reference word lines.   The semiconductor device according to claim 1, wherein the regular cell is a flash memory cell.