JPH10188586A - Semiconductor non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a DINOR type semiconductor non-volatile memory that achieves a simple circuitry and moreover, can carry out a fast and highly accurate data programming. SOLUTION: In the DINOR type flash memory, which performs a program operation by repeating operation a plurality of times through a verifying read action, program word line voltages (Vw)1-(Vw)a to be outputted from a stage voltage generating section 5 and reference bit line voltages (Vb)1-(Vb)k to be outputted from a stage voltage generating section 7 are both set to variable voltage values depending on the frequency of program while a data program is carried out so as to gradually increase a difference between the program work line voltages and the reference bit line voltages according to the progress in the frequency of programming.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically programmable semiconductor nonvolatile memory device, and
It relates to a data program system circuit in a semiconductor non-volatile memory device which performs data programming by injecting electrons into a floating gate by a Fowler-Nordheim (hereinafter, FN) tunnel phenomenon, such as an R (Divided bit line NOR) type flash memory. is there.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor nonvolatile memory device such as an EPROM or a flash memory, data is programmed by injecting electrons into a floating gate by channel hot electron (hereinafter, CHE) injection.
OR type semiconductor nonvolatile memory devices have been the mainstream.

However, the above-mentioned NOR type semiconductor nonvolatile memory device requires a large current at the time of CHE data programming, and it is difficult to supply this current from the on-chip booster circuit, and the power supply voltage will be reduced in the future. In that case, it is expected that it will be difficult to operate with a single power supply. Moreover, in the NOR type semiconductor nonvolatile memory device, data programming can be performed in units of bytes, that is, only up to about eight memory transistors at a time due to the above current limitation, and there is an extremely limited program speed. there were. In view of the above, a semiconductor non-volatile memory device that performs data programming by injecting electrons into the floating gate by the FN tunnel phenomenon, for example, a NAND
Type or DINOR type flash memory has been proposed.

FIGS. 6 (a) and 6 (b) respectively show NAND gates.
FIG. 2 is a diagram showing a memory array structure in a flash memory of the DINOR type.

[0005] For convenience, the NAND flash memory of FIG. 6A has a NAND string 1 connected to one bit line.
FIG. 9 is a diagram showing a memory array when four memory transistors are connected to a book.

In FIG. 6A, BL indicates a bit line, and two select transistors ST are connected to the bit line BL.
1, ST2, and four memory transistors MT1 to MT1.
A NAND string in which MT4s are connected in series is connected. The select transistors ST1 and ST2 are connected to select gate lines S
L1 and SL2, and the memory transistors MT1 to MT4 are controlled by word lines WL1 to WL4, respectively.

The DINOR type flash memory shown in FIG. 6B shows a DINOR memory array in which four memory transistors are connected to one sub-bit line SBL connected to one main bit line MBL for convenience. FIG.
In the DINOR type, the main bit line MBL and the sub bit line SBL are connected via a select transistor ST1 controlled by a select gate line SL. Sub-bit line SB
L intersects with four word lines WL1 to WL4, and four memory transistors MT1 to MT4 are arranged at each intersection position.

In the programming operation of such a NAND type or DINOR type flash memory, since the operating current at the time of data programming is small, it is relatively easy to supply this current from the booster circuit in the chip. There is an advantage that it is easy to operate. In addition, NAND
And DINOR type flash memories, it is possible to perform data programming in page units, that is, collectively for the memory transistors connected to the selected word line, due to the superiority of the operating current described above.
It is advantageous in terms of program speed. Further, in the above-described flash memory, even if program characteristics vary between memory transistors due to process variations or the like, the program operation is performed by repeating the program operation a plurality of times via the verify read operation. There is an advantage that variation in the program threshold voltage Vth can be suppressed.

In other words, when performing a page program for the memory transistors connected to the selected word line at a time, the page program data is transferred to a data latch circuit for each bit line, and the latch data of the program end cell is sequentially inverted to inhibit the program. By performing the state, a so-called bit-by-bit verify operation is performed, and excessive programming is prevented, and variation in the program threshold voltage Vth is suppressed.

[0010]

The above-mentioned N
The AND type and DINOR type flash memories have various advantages as described above, but have the following problems. That is, in the data programming operation of the flash memory, when the variation in the program characteristics due to the process variation or the like is large, the difference in the programming speed between the memory transistors connected to the selected word line becomes large, and the number of program / verify operations is reduced. Increase,
There is a problem that the program speed is limited.

[0011] This is because the variation in the programming speed due to the process variation or the like results in an empirical program time difference of about two digits between the memory transistors in the selected word line. value,
This is because, in the method of repeatedly applying a simple program pulse having the same pulse time width, the number of program / verify operations needs to be performed to about 100. In such a case, the time required for switching the voltage of the program operation / verify read becomes dominant rather than the substantial program voltage application time, and the programming speed is substantially impaired.

In order to avoid such a problem, it is necessary to perform data programming while suppressing the number of program / verify operations to a maximum of about 10 times. However, in order to perform this in the conventional repetitive application method of a simple program pulse having the same pulse voltage value and the same pulse time width, it is necessary to apply a program pulse having an increased pulse voltage value. In this case, there is a side effect that the variation of the program threshold voltage Vth in which the memory transistor having the fastest programming speed is excessively programmed increases.

A NAND which can solve the above-mentioned problem and can suppress the number of program / verify operations without increasing the variation of the program threshold voltage Vth.
A new programming method for a flash memory is disclosed in the following literature. Literature: "A 3.3V 32Mb NAND Flas
h Memory with Incremental
Step Pulse Programming S
cheme] '95 ISSCC p128 ~.

In the data program operation disclosed in the above-mentioned document, a high program word line voltage is applied to a selected word line and a reference bit line voltage is applied to a bit line, and the program word line voltage and the reference bit line voltage are applied. In the NAND flash memory that performs data programming, the program operation is performed by repeating the program operation a plurality of times through the verify read operation, and the program word line voltage gradually increases as the number of program increases. By setting the reference bit line voltage to a constant voltage value irrespective of the number of times of programming, the program voltage difference is gradually increased as the number of times of programming increases. , Program the data. That is, Incremental St
ep Pulse Programming method (hereinafter I
(SPP method). This ISPP method is D
The same can be applied to an INOR type flash memory.

FIG. 7 is a diagram showing NAN by the above-mentioned ISPP method.
FIG. 3 is a diagram showing a timing chart when data programming is performed on D-type and DINOR-type flash memories.
Hereinafter, the timing chart of FIG. 7 will be described step by step.

First, from time t1 to time t2, the page program data is synchronized with the page data transfer clock signal φCL in the data latch circuits 1 to 3 provided for each bit line.
m.

Next, from time t2 to time t4, the first program / verify operation is performed. That is, program / verify control signal φP / R
Controls the first program word line voltage VP
P1 (15V) and verify read word line voltage VR
(1.5 V) is alternately applied to the selected word line WSL. The reference bit line voltage GND (0 V) is applied to the selected bit line connected to the program memory transistor, and the intermediate inhibition power 1/2 VPP (8 V) is applied to the non-selected bit line connected to the non-program memory transistor.
As a result, the first program is completed by time t4, the latch data of the program end cell is inverted, and the program is inhibited from the next time.

From time t4 to t6, the second program / verify operation is performed, but is basically the same as the first program / verify operation. The difference is that the second program word line voltage V
PP2 (15.5 V) is to be incremented by 0.5 V from the first program word line voltage VPP1 (15 V).

From time t6 to time t8, a third program / verify operation is performed.
Third program word line voltage VPP3 (16 V)
Is incremented by 0.5V.

Finally, from time t9 to t11, the last q
This is the step of performing the 10th (eg, 10th) program / verify operation, in which the q-th program word line voltage VPPq (19.5 V) is applied, all programming is completed, and then all data latch circuits are turned off. Upon detecting that the data has become high level, the program operation ends.

Incidentally, the progress of the number of program times is not always limited to the final q-th one (for example, the tenth one). If it is detected that the data of all the data latch circuits have become high level, the program is automatically performed. To end.

In the data program operation according to the ISPP method, even if the threshold voltage Vth rises due to the progress of the programming of the memory transistor as the number of times of programming increases, the decrease in the floating gate potential due to this increases the program word. The electric field compensated by the voltage and applied to the tunnel oxide film of the memory transistor is kept constant. Therefore, the FN tunnel current value injected into the floating gate is always kept constant regardless of the increase in the number of times of programming, and the increase in the number of times of programming and the increase in the program threshold voltage Vth have a linear relationship. As a result, it is possible to control the program threshold voltage Vth more accurately while suppressing the number of program / verify operations.

On the other hand, the same pulse voltage value
In the data program operation by the repetitive application method of the simple program pulse having the same pulse time width, when the programming of the memory transistor progresses as the number of times of programming increases and the threshold voltage Vth rises,
This lowers the floating gate potential,
The electric field applied to the tunnel oxide of the memory transistor decreases. Therefore, the value of the FN tunnel current injected into the floating gate gradually decreases as the number of times of programming increases, and the saturation phenomenon of the program threshold voltage Vth becomes remarkable as the number of times of programming increases. The rising value of the program threshold voltage Vth has a logarithmic relationship. As a result, it is difficult to control the program threshold voltage Vth with high accuracy while suppressing the number of program / verify operations. When the program voltage value is increased, side effects such as excessive programming are caused.

The above-described data program operation by the ISPP method is a very excellent programming method in that the control of the number of program / verify operations and the high-precision program control are compatible. However, in the data program operation by the ISPP method, it is necessary to generate a program word line voltage whose voltage value changes stepwise in a direction gradually increasing as the number of times of programming increases.

A specific example of such a program word line voltage generating circuit is disclosed in the following literature. Reference: IEEE JOURNAL OF SOLID-
STATE CIRCUITS, VOL. 30, NO.
11, NOVEMBER 1995 p1152 in FIG. 7 is a circuit example.

However, the program word line voltage generating circuit disclosed in the above document requires a high voltage of about 20 V, so that the voltage value of the program word line voltage is increased by the high voltage source generated by the booster circuit. It is necessary to generate the program word line voltage that changes step by step. Therefore, when it is necessary to gradually increase the stepwise change of the program word line voltage more finely and in multiple steps, the configurations of the booster circuit and the program word line voltage generating means whose voltage value changes stepwise are not simple.

For example, as an example corresponding to the above problem, 1
An example in which the ISPP method is applied to a so-called multi-level NAND flash memory in which 2-bit digital data is recorded in individual memory transistors is disclosed in the following literature. Literature: “A 3.3V 128Mb Multi-Le
Bel NAND Flash Memory for
Mass Storage Application
s "'96 ISCC p32-p33.

In the above-mentioned reference example, in order to suppress the Vth distribution of each state required for a multi-valued memory to be narrow, the program word line voltage is set to 0.1V from 14.5V to 21V.
The ISPP method of changing in 2V steps is adopted.
Therefore, in this case, it is necessary to generate a program word line voltage whose voltage value changes stepwise in as many as 32 steps.

The above-described circuit for generating a program word line voltage can be applied to a DINOR type flash memory. In this case, the DINOR type flash memory has the same disadvantages as described above, and has a simple structure and high accuracy. It is difficult to achieve.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the same effects as the ISPP method, with a simple circuit configuration, high-speed and high-precision data programming. It is an object of the present invention to realize a DINOR type semiconductor nonvolatile memory device that can perform the above-described operations.

[0031]

To achieve the above object, the present invention comprises a plurality of memory transistors arranged in a matrix, wherein a main bit line is hierarchized into sub-bit lines,
DI with memory cell transistor connected to sub-bit line
A NOR transistor is formed, and memory transistors arranged on the same row are connected to a common word line. A high program word line voltage is applied to the word line to which the memory transistor is connected, and a reference bit line voltage is applied to the bit line. A DINOR type semiconductor nonvolatile memory device for electrically programming data in said memory transistor by a program voltage difference between said program word line voltage and a reference bit line voltage, wherein said memory transistor is programmed a plurality of times through a verify read operation. Means are provided for repeating the operation, setting both the program word line voltage and the reference bit line voltage to variable voltage values according to the number of times of programming, and gradually increasing the program voltage difference as the number of times of programming increases.

The DINOR type semiconductor nonvolatile memory device further comprises a data latch circuit provided for each bit line, and page program data to be collectively performed by memory transistors connected to a selected word line, to the data latch circuit. Means for transferring, and means for supplying a program inhibit bit line voltage set to a voltage value lower than the program word line voltage and higher than the reference bit line voltage to the data latch circuit during a program operation.

Further, in the DINOR type semiconductor nonvolatile memory device, the program word line voltage increases stepwise at every predetermined number of times of programming in units of progress of a predetermined number of times of programming. The voltage value decreases step by step for each single program constituting the predetermined program count, and the voltage change is repeated at the same voltage for each predetermined program count.

Further, in the DINOR type semiconductor nonvolatile memory device, the reference bit line voltage is stepwise reduced in voltage value every predetermined number of times of programming in units of progress of a predetermined number of times of programming. The voltage value increases stepwise for each single program that constitutes the predetermined program count, and the corresponding change is repeated at the same voltage for each predetermined program count.

In the DINOR type semiconductor nonvolatile memory device, the program word line voltage is a boosted voltage boosted by a booster circuit, and the reference bit line voltage is a divided voltage within a power supply voltage range. Voltage.

According to the DINOR type semiconductor nonvolatile memory device of the present invention, for example, the program word line voltage greatly increases stepwise every predetermined number of times of about several times, while the reference bit line voltage increases. Is set so that the voltage value gradually decreases and decreases step by step for each single program, and the same voltage change is repeated every predetermined program. Therefore, even though the number of changes of each of the two voltages is small, the substantial number of changes of the substantial program voltage difference can be increased, and the circuit for generating the program word line voltage and the reference bit line voltage is constituted by a simple circuit. It can be preferred.

Alternatively, in the DINOR type semiconductor non-volatile memory device according to the present invention, the reference bit line voltage greatly decreases stepwise at every predetermined number of program times of about several times, while the program word line voltage decreases. The voltage value is set so that the voltage value increases stepwise and gradually with each single program count, and the voltage change is the same every predetermined program count. Therefore, even though the number of changes of each of the two voltages is small, the substantial number of changes of the substantial program voltage difference can be increased, and the circuit for generating the program word line voltage and the reference bit line voltage is constituted by a simple circuit. It can be preferred.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a specific configuration example of a semiconductor nonvolatile memory device according to the present invention, more specifically, a data program system circuit of a DINOR type flash memory.

In FIG. 1, reference numeral 1 denotes a memory array,
The m bit lines B1 to Bm are wired. Each of the bit lines B1 to Bm has n DINORs.
Each DINOR column is composed of two selection transistors (□ in the figure) and j memory transistors (O in the figure). That is, the memory array 1 includes DINOR columns S11 to Snm. SL11-SL
n1, SL12 to SLn2 indicate selection gate lines for controlling the selection transistors, and WL11 to WLnj indicate word lines for controlling the memory transistors.

SA1 to SAm indicate data latch circuits provided corresponding to the respective bit lines B1 to Bm. The supply power of the data latch circuits SA1 to SAm is such that the cathode side is connected to (VB) L and the anode side is connected to (VB) H. At the time of data programming, (VB) L is powered according to the progress of k (k = 1 to 5). Voltage (VCC = 3.
3V), the reference bit line voltage (Vb) 1 gradually decreasing within the range of
To (Vb) k, (VB) H is set to the intermediate inhibition voltage 1/2 VPP (for example, 8 V).

Reference numeral 2 denotes a main row decoder. The main row decoder 2 decodes the upper X1 to Xa of the X input, outputs the output voltages of the selection gate lines SL11 to SLn1, SL12 to SLn2, and the DINOR column selection signal x1 to Xn. xn.

Reference numeral 3 denotes a sub-decoder.
Decodes the upper X1 to Xb of the X input and selects the selected DI
The word line voltages V1 to Vj in the NOR column are generated.
The word line voltages V1 to Vj at the time of data programming are the program word line voltages (V) in which the selected word line voltage is raised to a high voltage that gradually increases as s progresses (s = 1 to 5).
w) The unselected word line voltage is set to one of (1) to (Vw) s to the intermediate inhibition voltage 1/2 VPP (for example, 8 V).

Reference numeral 4 denotes a local decoder. The local decoder 4 includes transmission circuits T11 to Tnj corresponding to the respective word lines WL11 to WLnj, and includes a DINOR column selection signal x.
1 to xn are selected in DINOR column units. Each of the transmission circuits T11 to Tnj outputs the word line voltages V1 to Vj to the corresponding word line when selected by the DINOR column selection signal, and operates when not selected by the DINOR column selection signal. And outputs an appropriate voltage value (for example, ground voltage GND) to the corresponding word line.

Reference numeral 5 denotes a program word line voltage generator.
= 1 to 5), and generates and outputs program word line voltages (Vw) 1 to (Vw) s which are boosted to high voltages gradually increased by control signals φ1 to φs.

Reference numeral 6 denotes a program word line voltage control unit. The program word line voltage control unit 6 controls the progress of s (k
= 1 to 5), the control signals φ1 to φs are output.

Reference numeral 7 denotes a reference bit line voltage generator. The reference bit line voltage generator 7 controls the power supply voltage (VCC) by control signals φ1 to φk in accordance with the progress of k (k = 1 to 5).
= 3.3V), and generates and outputs the reference bit voltages (Vb) 1 to (Vb) k that gradually decrease within the range.

Reference numeral 8 denotes a reference bit line voltage controller. The reference bit line voltage controller 8 outputs the control signals φ1 to φk as k progresses (k = 1 to 5).

Reference numeral 9 denotes a column decoder. The column decoder 9 decodes the Y inputs Y1 to Yc, and selects an arbitrary one of the bit lines B1 to Bm by the column selection unit 10.
The column address at the time of transferring the page program data is sequentially incremented in synchronization with the page data transfer signal φCK.
The page program is serially transferred to SAm sequentially.

In the first DINOR type flash memory of the present invention shown in FIG. 1, the program word line voltage gradually increases in accordance with the progress of s (k = 1 to 5), while the reference bit line voltage increases by k. It is set so as to gradually decrease in accordance with the progress (k = 1 to 5). Therefore, even though the number of changes of both voltages is as small as s = k = 5, the actual number of gradually increasing changes in the program voltage difference can be increased to s × k = 25 by a combination.

FIG. 2 is a diagram showing an example of a specific circuit configuration of the program word line voltage generator 5 in the specific example of the configuration of the first DINOR type flash memory of FIG.

In FIG. 2, reference numeral 5a denotes a booster circuit. The booster circuit 5a is driven by a complementary clock signal output from the oscillation circuit 5b and outputs a boosted voltage VPP.

Reference numeral 5c denotes a resistance dividing unit.
Outputs the divided voltage Va by connecting the resistance element R0 in series with any of the resistance elements R1 to Rk via the transfer gates T1 to Tk controlled by the control signals φ1 to φk.

Reference numeral 5d denotes a reference voltage generation circuit. The reference voltage generation circuit 5d generates a reference voltage Vref. Reference numeral 5e denotes a comparator. The comparator 5e outputs a comparison output C-out between the divided voltage Va and the reference voltage Vref by the resistance dividing unit 5c, and when the divided voltage Va becomes larger than the reference voltage Vref, the oscillation circuit 5b Stop and re-activate when smaller. The program word line voltages (Vw) 1 to (Vw) s output in this manner theoretically have the following voltage values.

[0054]

(Vw) _1-s = Vref × {1+ (R ₀ / R _1−s )} (1)

Therefore, by setting the resistance values R _{0 to} R _s of the resistance elements R _{1 to} Rs in such a manner as to gradually decrease as the s progresses (k = 1 to 5), the program word line voltages (Vw) 1 to (Vw) 1 to ( Vw) s can be gradually increased.

FIG. 3 is a diagram showing an example of a specific circuit configuration of the reference bit line voltage generator 7 in the configuration example of the DINOR type flash memory of FIG.

In FIG. 3, between the power supply voltages (VCC [3.
3V] to GND [0V]) are divided by the resistance elements R0 to Rk connected in series to generate reference bit line voltages (Vb) 1 to (Vb) k. Further, each of the reference bit line voltages (Vb) 1 to (Vb) k is
Through k, the reference bit line voltages (Vb) 1 to (Vb) k gradually decreasing according to the progress of k (k = 1 to 5) under the control of control signals φ1 to φk, and a buffer BUF having a voltage follower configuration Output via

FIG. 4 is a diagram showing a timing chart in the first data programming method in the configuration example of the DINOR type flash memory according to the present invention of FIG.

In this case, the program word line voltage (V
w) 1 to (Vw) s are incremented by s every time the number of times of programming is five, the program word line voltage value is increased stepwise by 1 V each time, and s = 1 to 5 Then, the voltage value gradually increases from (Vw) 1 to (Vw) s = 15V to 19V.

On the other hand, reference bit line voltages (Vb) 1 to (V
b) k is incremented by k for each single program, the reference bit line voltage value is gradually decreased by 0.2 V each time, and (Vb) 1 to
(Vb) The voltage value gradually decreases from k = 0.8V to 0V. The voltage change is repeated at the same voltage as s = 1 to 5 progresses.

Therefore, in the first data programming method, the combination of s and k causes the program voltage difference to gradually increase from 14.2 V to 19 V in steps of 0.2 V every time the number of times of single programming is increased.

Hereinafter, a timing chart of the first data programming method of FIG. 4 will be described step by step with reference to the configuration example of FIG.

First, from time t1 to time t2, page program data is synchronized with the page data transfer clock signal φCL in the data latch circuits 1 to 3 provided for each bit line.
m.

Next, from time t2 to time t3, s = 1
This is a step of performing five program / verify operations of k = 1 to 5. In other words, program word line voltage (Vw) 1 = 15 V and verify read word line voltage VR = 1.5 V are alternately applied to the selected word line WSL five times under the control of the program / verify control signal φP / R. In addition, the progress of the number of programs (k =
Reference bit line voltages (Vb) 1 to (Vb) k = 0.8 V to 0 V, which gradually decrease by 0.2 V together with 1 to 5), are applied to the unselected bit lines to which the non-program memory transistors are connected. Is the intermediate inhibition voltage 1/2 VPP (8
V) is applied. As a result, a program voltage difference (14.2 V to 15 V) that increases stepwise by 0.2 V with the progress of the program count (k = 1 to 5) is applied to the program memory transistor, and the latch data of the program end cell is Is inverted and the program is prohibited from the next time.

From time t3 to time t4, s = 2 and k = 1 to 5 for performing the program / verify operation five times. Basically, when s = 1 described above, Is the same as The difference is that the program word line voltage increases by 1V from (Vw) 1 = 15V to (Vw) 2 = 16V. As a result, the program voltage difference (1
(5.2V to 16V) continuously increases in steps of 0.2V.

The same operation is repeated, and between the time t5 and the time t6, the final s = 5 and k = 1 to 5 program / verify operations are performed five times.
A program word line voltage (Vw) 5 = 19 V is applied, and the program voltage difference (18.2 V to 19 V) increases step by step by 0.2 V as the number of program times progresses (k = 1 to 5).

It should be noted that the progress of the number of programs is not always performed until the last s = k = 5. When it is detected that the data of all the data latch circuits have become high level, the program is automatically performed. finish.

As explained above, the DINOR of the present invention
According to the first data programming method in the flash memory of the type, the program word line voltage is greatly increased stepwise at every predetermined number of times of about several times, while the reference bit line voltage is Each time, the voltage value is set so that the voltage value gradually decreases gradually and the same voltage value is repeated every predetermined number of programs. Therefore, even if the number of changes of both voltages is small, the substantial program voltage difference can increase the number of changes gradually, and the number of generations of the program word line voltage and the reference bit line voltage can be reduced by a simple circuit. It can be constituted and is suitable.

FIG. 5 shows the DINOR according to the present invention of FIG.
FIG. 5 is a diagram showing a timing chart in a second data programming method in a configuration example of a flash memory.

In this case, the reference bit line voltages (Vb) 1 to
(Vb) k is incremented every time the number of program operations is five, and the reference bit line voltage is set to 0.5 each time.
V gradually decreases, and for k = 1 to 5 progression, (V
b) 1 to (Vb) The voltage value gradually decreases to k = 2V to 0V.

On the other hand, the program word line voltage (Vw) 1
（(Vw) s, s is incremented by the number of times of single program, and each time the program word line voltage is 0.1 V
S = 1 to 5 (V
w) The voltage value gradually increases from 1 to (Vw) 2 = 17V to 17.4V. The voltage change is repeated at the same voltage as k = 1 to 5 progresses.

Therefore, in the second data programming method, the program voltage value gradually increases in steps of 0.1 V from 15.0 V to 17.4 V every time the single program is performed by the combination of k and s. .

The timing chart of the second data programming method shown in FIG. 5 will be described step by step with reference to the configuration example shown in FIG.

First, from time t1 to time t2, page program data is supplied in synchronization with page data transfer clock signal φCK to data latch circuits 1 to 3 provided for each bit line.
m.

Next, from time t2 to time t3, k = 1
This is a step of performing five program / verify operations of s = 1 to 5. That is, the program / verify control signal φP / R controls the program word line voltage and the verify read word line voltage VR = 1.5 V
Are alternately applied to the selected word line WSL five times, and the program word line voltage becomes (Vw) 1 to (Vw) s = 17 V to 17.
It increases stepwise by 4V and 0.1V. The reference bit line voltage (Vb) is applied to the selected bit line to which the program memory transistor is connected, regardless of the progress of the number of programming.
1 = 2V is applied, and the non-selected bit line to which the non-program memory transistor is connected has the intermediate inhibition voltage of 1 / 2V
PP (8V) is applied. As a result, a program voltage difference (15 V to 15.4 V) that increases stepwise by 0.1 V with the progress of the number of program times (s = 1 to 5) is applied to the program memory transistor, and the latch data of the program end cell is Is inverted and the program is prohibited from the next time.

From time t3 to time t4, the step of performing five program / verify operations of k = 2 and s = 1 to 5 is basically the same as the above-described case of k = 1. The difference is that the reference bit line voltage is (V
b) 0.5V from (Vb) 1 = 2V to 2 = 1.5V
Is to decrease. As a result, the program voltage difference (15.5) increases with the progress of the number of programs (s = 1 to 5).
V to 15.9 V) continuously increases in steps of 0.1 V.

By repeating the same operation, from time t5 to t
Step 6 is a step in which the final k = 5 and s = 1 to 5 for five program / verify operations. A reference bit line voltage (Vb) of 5 = 0 V is applied, and the program voltage difference (17 V to 17.4 V) increases stepwise by 0.1 V as the number of times of programming progresses (s = 1 to 5).

The progress of the number of programming is not always limited to the last k = s = 5. If it is detected that the data of all the data latch circuits have become high level, the program is automatically performed. finish.

As described above, the DINOR of the present invention
According to the second data programming method in the flash memory of the type, the reference bit line voltage is greatly reduced stepwise at every predetermined number of program times of about several times, while the program word line voltage is reduced by a single program number. Each time, the voltage value is set so as to gradually increase and decrease, and the same voltage change is repeated every predetermined number of programs. Therefore, even though the number of changes in each of the two voltages is small, the number of substantial changes in the substantial program voltage difference can be increased, and the circuit for generating the program word line voltage and the reference bit line voltage is a simple circuit. It can be constituted and is suitable.

As described above, the DINOR of the present invention
According to the flash memory, data programming is performed by a program voltage difference between a program word line voltage and a reference bit line voltage, and both the program word line voltage and the reference bit line voltage are set to variable voltage values according to the number of times of programming. And the program voltage difference gradually increases as the number of times of programming increases. Therefore, substantially the same effect as the ISPP method can be obtained, and high-speed and high-precision data programming can be performed. Moreover, since both the program word line voltage and the reference bit line voltage are variable,
Even in the case where the gradual change of the program voltage difference is a multi-step change, a circuit for realizing this is a circuit for increasing only the high program word line voltage.
With the SPP method, the configuration can be made much easier.

In the above description, for convenience,
Although the description has been given mainly of the DINOR type flash memory, it goes without saying that the present invention can be applied to other semiconductor nonvolatile memory devices that perform data programming by injecting electrons into the floating gate by the FN tunnel phenomenon.

[0082]

As described above, according to the present invention,
A DINOR-type semiconductor nonvolatile memory device having substantially the same efficiency as the ISPP method, and having a simple circuit configuration and capable of performing high-speed and high-accuracy data programming can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a specific configuration example at the time of a first DINOR type flash memory data program operation according to the present invention.

FIG. 2 is a diagram showing an example of a specific circuit configuration of a program word line voltage generator in the DINOR type flash memory of FIG. 1;

FIG. 3 is a diagram showing an example of a specific circuit configuration of a reference bit line voltage generator in the DINOR type flash memory of FIG. 1;

FIG. 4 is a diagram showing a timing chart of a first data programming method in the DINOR type flash memory of FIG. 1;

FIG. 5 is a diagram showing a timing chart of a second data programming method in the DINOR type flash memory of FIG. 1;

FIG. 6 is a diagram showing a memory array structure in a DINOR type flash memory.

FIG. 7 is a diagram showing a timing chart when data programming of a DINOR type flash memory is performed by a conventional ISPP method.

[Explanation of symbols]

SL11 to SLn2 ... select gate line, W11 to Wnj ... word line, B1 to Bm ... bit line, X1 to Xa, X1 to Xb ...
X input, Y1 to Yc ... Y input, V1 to Vj ... select DIN
OR column word line voltage, x1 to xn... DINOR column selection signal, T11 to Tnj... Word line voltage transmission circuit, S11 to Snm.
DINOR column, SA1 to SAm ... data latch circuit,
(VB) H: anode power supply (data latch circuit), (VB)
L: Cathode power supply (data latch circuit), VPP: Boost voltage, 1/2 VPP: Intermediate inhibition voltage, VPP1 to VPPq
... first to q-th program word line voltages (Vw)
1 to (Vw) s: 1st to sth program word line voltage, (Vb) 1 to (Vb) k: 1st to kth reference bit line voltage, φ1 to φs: 1st to sth The first control signal, φ1 to φk... The first to kth control signals, T1 to T
s: first to s-th transfer gates, T1 to Tk: first to first
K-th transfer gate, R0 to Rs, R0 to Rk... Voltage dividing resistance elements, Vref... Reference voltage, Va.
φ￣: complementary clock signal (boost circuit), φCL: page data transfer clock signal, φP / R: program / verify control signal, ST1 to ST2: selection transistor,
MT1 to MT4: memory transistor, 1: memory array, 2: main row decoder, 3: sub row decoder,
4 Local row decoder 5 Program word line voltage generator 5a Boost circuit 5b Oscillator 5c Resistor divider 5d Reference voltage generator 5e Comparator 6
... Program word line voltage control unit, 7 ... reference bit line voltage generation unit, 8 ... reference bit line voltage control unit, 9 ... column decoder, 10 ... column selection unit.

Claims (5)

[Claims] A plurality of memory transistors arranged in a matrix, wherein a main bit line is hierarchized into sub-bit lines;
DI with memory cell transistor connected to sub-bit line
A NOR transistor is formed, and memory transistors arranged on the same row are connected to a common word line. A high program word line voltage is applied to the word line to which the memory transistor is connected, and a reference bit line voltage is applied to the bit line. A DINOR type semiconductor nonvolatile memory device for electrically programming data in the memory transistor by a program voltage difference between the program word line voltage and a reference bit line voltage, wherein a plurality of program operations are performed through a verify read operation. Means for repeating the operation, setting both the program word line voltage and the reference bit line voltage to variable voltage values according to the number of times of programming, and gradually increasing the program voltage difference as the number of times of programming increases
INOR type semiconductor nonvolatile memory device. 2. A data latch circuit provided for each bit line, means for transferring page program data to be collectively performed on memory transistors connected to a selected word line to the data latch circuit, and the data latch circuit during a program operation. 2. The DI according to claim 1, further comprising: means for supplying a program inhibit bit line voltage set to a voltage value lower than the program word line voltage and higher than the reference bit line voltage.
NOR type semiconductor nonvolatile memory device. 3. The program word line voltage gradually increases in voltage every predetermined number of times of programming in units of progress of the number of times of programming, and the reference bit line voltage is a single program number constituting the predetermined number of times of programming. 2. The method according to claim 1, wherein the voltage value decreases step by step every time, and the voltage change is repeated at the same voltage every predetermined number of times of the program.
INOR type semiconductor nonvolatile memory device. 4. The voltage value of the reference bit line voltage decreases step by step at every predetermined number of times of programming in units of progress of a predetermined number of times of programming, and the program word line voltage is a unit voltage constituting the predetermined number of times of programming. 2. The DINOR type semiconductor nonvolatile memory device according to claim 1, wherein the voltage value is increased stepwise every time the program is executed, and the change is repeated at the same voltage every time the predetermined program is executed. 5. The DINOR type according to claim 1, wherein the program word line voltage is a boosted voltage boosted by a booster circuit, and the reference bit line voltage is a divided voltage divided within a power supply voltage range. Semiconductor nonvolatile storage device.