KR100944322B1 - Phase change memory device - Google Patents

Abstract

The present invention relates to a phase change memory device, and discloses a technique of improving the sensing voltage margin by driving the voltage level of the bit line clamp signal to the overdrive voltage level in the read mode.

Specifically, the present invention includes a cell array including a phase change resistance element and a read / write of data, a sensing voltage adjusting unit outputting a bit line clamp signal at an overdrive voltage level in a first section of a read mode, and the cell array A phase change memory device including a sense amplifier configured to compare and amplify a sensing voltage and a reference voltage applied from the control panel, and to control a range of sensing voltage levels according to the bit line clamp signal.

Description

Phase change memory device {PHASE CHANGE MEMORY DEVICE}

The present invention relates to a phase change memory device for driving a voltage level of a bit line clamp signal to an overdrive voltage level in a read mode to improve a sensing voltage margin. More specifically, the sensing voltage margin is improved by driving the voltage level of the bit line clamp signal to the overdrive voltage level in the first section of the read mode and then driving the voltage level of the bit line clamp to a lower normal voltage level in the second section after the first section. Associated with a phase change memory device.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the electrical conduction state due to the change in resistance.

Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a compound (Chalcogenide) mainly composed of chalcogen elements (S, Se, Te), specifically, a germanium antimony tellurium alloy material (Ge2Sb2Te5) consisting of Ge-Sb-Te ).

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 becomes a crystalline phase and becomes a material of a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, when the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

In the conventional phase change memory device, there is a problem in that the reset and the set cannot be clearly distinguished based on the reference voltage because sufficient sensing voltage margin is not secured between the sensing voltage in the case of the reset and the set.

In order to solve the above problems, the present invention discloses a phase change memory device for driving a voltage level of a bit line clamp signal to an overdrive voltage level in a read mode to improve a sensing voltage margin.

A phase change memory device of the present invention for achieving the above object is a cell array including a phase change resistance element and the read / write of data, the bit line clamp signal to the overdrive voltage level in the first section of the read mode Disclosed is a phase change memory device including a sensing voltage adjusting unit outputting a sensing amplifier and a sense amplifier for comparing and amplifying a sensing voltage and a reference voltage applied from the cell array, and controlling a range of sensing voltage levels according to the bit line clamp signal. do.

The present invention has the advantage that the difference between the sensing voltage in the case of reset and set can be increased by driving the bit line clamp signal to the overdrive voltage. That is, by increasing the margin of the sensing voltage, the sensing voltage in the case of reset and the sensing voltage in the case of a set can be easily distinguished based on the reference voltage.

Preferred embodiments of the present invention are for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications, changes, etc. are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

4 is a circuit diagram of a cell array and a column switching unit of a phase change memory device according to the present invention.

The present invention includes a cell array CA and a column switching unit YSW. Here, it is preferable that the column switching unit YSW consists of a plurality of PMOS transistors SW1 to SW4. In the embodiment of the present invention, the configuration of the column switching unit YSW has been described as a PMOS transistor, but the present invention is not limited thereto, and may be implemented as an NMOS transistor.

The cell array CA includes a plurality of unit cells C formed at regions where the bit line BL and the word line WL cross each other. The unit cell C includes a phase change resistance element PCR and a diode D. Here, the diode D is made of a PN diode element.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL.

In the present invention, a low voltage is applied to the selected word line WL in the read mode. The read voltage Vread is applied to the bit line BL so that the set read current Iset or the reset read current Ireset flows toward the word line WL through the bit line BL, the phase change resistance element PCR and the diode D.

In addition, the PMOS transistors SW1 to SW4 are connected between the bit line BL and the global bit line GBL so that the column select signals LY1_m to LY4_m are applied through the gate terminal. In this case, the present invention forms a hierarchical bit line structure by connecting a plurality of bit lines BL to one global bit line GBL.

The PMOS transistors SW1 to SW4 are selectively turned on according to the column selection signals LY1_m to LY4_m to control the connection between the bit line BL and the global bit line GBL. In the active mode, only one of the column selection signals LY1_m to LY4_m is activated to select the unit cell C connected to the corresponding bit line BL.

5 is a block diagram illustrating a phase change memory device according to the present invention.

The phase change memory device of the present invention includes the sensing voltage adjusting unit 100, the sense amplifiers SA_1, SA_2,..., SA_N, the write driver W / D_1, W / D_2,..., W / D_N and the main circuit. The reference voltage supply unit 300 is included.

Each of the sense amplifiers SA_1, SA_2,..., SA_N includes sensing current voltage converting units 200_1, 200_2,..., 200_N and amplifiers A_1, A_2,..., A_N. Each of the sense amplifiers SA_1, SA_2, ..., SA_N senses cell data applied via the global bit lines GBL_1, GBL_2, ... GBL_N and compares the data "1" and data "with reference voltage VREF. 0 "is distinguished.

The sensing current voltage converter 200 included in the sense amplifier SA converts the cell sensing current flowing through the global bit line GBL into a voltage according to the bit line clamp signal BL_CLMP and outputs the sensing voltage VDAT. The sensing current voltage converter 200 is limited in the value of the sensing current according to the bit line clamp signal BL_CLMP. The bit line clamp signal BL_CLMP is commonly applied to each of the plurality of sense amplifiers SA_1, SA_2,..., SA_N.

 The main reference voltage supply unit 300 outputs a reference voltage VREF which is a reference for distinguishing cell data sensed by a memory cell during a read operation.

The amplifier A compares and amplifies the sensing voltage VDAT output from the sensing current voltage converter 200 and the reference voltage VREF, and outputs the amplified voltage to the input / output bus IO_BUS. The write driver W / D outputs a driving voltage corresponding to the input data applied from the input / output bus IO_BUS to the global bit line GBL when writing data to the cell.

The sensing voltage adjusting unit 100 outputs the bit line clamp signal BL_CLMP at the overdrive voltage level in the first section of the read mode and the normal voltage lower than the overdrive voltage level at the second section after the first section. Output to the level.

6 is a detailed circuit diagram of the sensing current voltage converter 200 according to the present invention.

The sensing current voltage converter 200 includes a precharge unit 210, a sensing current supply adjuster 220, a clamp voltage adjuster 230, a clamp voltage precharge controller 240, and a clamp voltage precharge unit 250. ).

The precharge unit 210 includes a PMOS transistor P2. The PMOS transistor P2 is connected between the high voltage VPPSA applying terminal and the sensing voltage VDAT output terminal to receive the precharge signal PRE_VDAT through the gate terminal.

In addition, the sensing current supply adjuster 220 includes a PMOS transistor P3. The PMOS transistor P3 is connected between the high voltage VPPSA applying stage and the sensing voltage VDAT output stage to receive the bit line clamp signal BL_CLMP through the gate terminal.

The clamp voltage adjuster 230 includes an NMOS transistor N3. The NMOS transistor N3 is connected between the output terminal of the sensing voltage VDAT and the global bit line GBL to apply the bit line clamp signal BL_CLMP through the gate terminal.

The clamp voltage precharge control unit 240 includes a PMOS transistor P4. The PMOS transistor P4 is connected between the power supply voltage VDD applying stage and the NMOS transistor N4 to apply the bit line clamp signal BL_CLMP through the gate terminal.

The clamp voltage precharge unit 250 includes an NMOS transistor N4. The NMOS transistor N4 is connected between the PMOS transistor P4 and the global bit line GBL to receive the precharge signal PRE_CLMP through the gate terminal.

An operation related to the sensing current voltage converter 200 having such a configuration will be described below.

The precharge unit 210 precharges the sensing voltage VDAT to the high voltage VPPSA level before the PMOS transistor P2 is turned on when the precharge signal PRE_VDAT is activated to output the sensing voltage VDAT.

The sensing current supply adjusting unit 220 controls the sensing voltage VDAT by adjusting the amount of the sensing current iSEN flowing in the PMOS transistor P3 according to the bit line clamp signal BL_CLMP. Here, the sensing current iSEN is controlled by the bit line clamp signal BL_CLMP.

The sensing current supply adjusting unit 220 converts the sensing current of the cell applied from the global bit line GBL into the sensing voltage VDAT.

When the sensing mode is activated, the sensing current of the cell is represented by the sensing current iSEN flowing through the sensing current supply adjusting unit 220. Before the sensing mode is activated, the global bit line GBL is precharge clamp voltage according to the precharge unit 210, the clamp voltage adjuster 230, the clamp voltage precharge controller 240, and the clamp voltage precharge unit 250. Precharged to VPRE_CLMP level.

The clamp voltage adjuster 230 adjusts the global bitline GBL to the overdrive voltage VCLMP_H level according to the bitline clamp signal BL_CLMP. The clamp voltage precharge control unit 240 precharges the global bitline GBL to the power supply voltage VDD level before the bitline clamp signal BL_CLMP is activated. Here, the bit line clamp signal BL_CLMP is a signal for controlling the sensing voltage applied from the cell through the global bit line GBL.

The clamp voltage precharge unit 250 precharges the global bit line GBL to the power supply voltage VDD level according to the precharge signal PRE_CLMP.

That is, when the bit line clamp signal BL_CLMP is inactivated to a low level, the PMOS transistor P4 is turned on to precharge the global bit line GBL to the power supply voltage VDD level. At this time, when the precharge signal PRE_CLMP is activated, the NMOS transistor N4 is turned on to supply the power supply voltage VDD to the global bit line GBL. Here, the power source voltage VDD is a power source supplied from the outside.

On the other hand, when the bit line clamp signal BL_CLMP is activated to a high level, the NMOS transistor N3 is turned on to reach the overdrive voltage VCLMP_H level.

7 is an operation timing diagram of the sensing current voltage converter 200 according to the present invention.

Referring to FIG. 7, in the precharge period t0, the word line WL, the precharge signal PRE_VDAT, the bit line clamp signal BL_CLMP, the precharge signal PRE_CLMP, and the global bit line GBL maintain the ground voltage GND level.

When the precharge signal PRE_VDAT is activated at a low level, the PMOS transistor P2 is turned on to precharge the sensing voltage VDAT to the high voltage VPPSA level before the sensing voltage VDAT is output.

When the bit line clamp signal BL_CLMP is at the low level, the PMOS transistor P4 is turned on to precharge the clamp voltage precharge unit 250 to the power supply voltage VDD level. At this time, when the bit line clamp signal BL_CLMP is at a low level, the NMOS transistor N3 is maintained in a turned off state. As a result, the global bit line GBL maintains the ground voltage GND level.

In the read mode period t1, the word line WL, the precharge signal PRE_VDAT, and the bit line clamp signal BL_CLMP maintain the ground voltage GND level. Then, the precharge signal PRE_CLMP transitions to the precharge clamp voltage VPRE_CLMP level. Accordingly, the voltage level of the global bit line GBL gradually increases according to the power supply voltage VDD level applied from the clamp voltage precharge control unit 240.

The read mode section t2 is represented by a first section (overdrive section), in which the bit line clamp signal BL_CLMP transitions from the ground voltage GND level to the overdrive voltage VCLMP_H level.

In addition, the word line WL transitions to the pumping voltage VPP level in the first section. Accordingly, the NMOS transistor N3 is turned on so that the voltage level of the global bit line GBL is higher than the t1 section. At this time, when the bit line clamp signal BL_CLMP transitions to the overdrive voltage VCLMP_H level, the sensing voltage VDAT draws a voltage level curve falling from the high voltage VPPSA to the power supply voltage VDD level.

The read mode section t3 is represented by a second section in which the bit line clamp signal BL_CLMP transitions (discretely falls) from the overdrive voltage VCLMP_H level to the normal voltage VCLMP_L level. The normal voltage VCLMP_L level is set lower than the overdrive voltage VCLMP_H level and higher than the ground voltage GND level.

Also, in the second section, the precharge signal PRE_CLMP transitions from the precharge clamp voltage VPRE_CLMP level to the ground voltage GND level. Accordingly, the NMOS transistor N4 is turned off so that the global bit line GBL maintains the read voltage Vread level. In this case, the global bit line GBL has a different read voltage Vread level in case of reset and case of set.

Since the bit line clamp signal BL_CLMP maintains the overdrive voltage VCLMP_H level in the first section, the sensing current iSEN flows less by the PMOS transistor P3. Since the reset operation is performed when the sensing current iSEN flows less, the read voltage Vread_RESET when the read voltage Vread for the sensing current iSEN is reset. Therefore, the read voltage Vread_RESET in the case of reset becomes the voltage level VCLMP_H-Vth equal to the overdrive voltage VCLMP_H level, which is the voltage level of the bit line clamp signal BL_CLMP, minus the threshold voltage Vth of the NMOS transistor N3.

In the second section, since the bit line clamp signal BL_CLMP transitions from the overdrive voltage VCLMP_H level to the normal voltage level VCLMP_L, the sensing current iSEN flows more by the PMOS transistor P3 than the second section. Since the set operation is performed when the sensing current iSEN flows a lot, the read voltage Vread_SET when the read voltage Vread for the sensing current iSEN is set is set. Therefore, the read voltage Vread_SET in the case of the set becomes the voltage level VCLMP_L-Vth equal to the normal voltage VCLMP_L level, which is the voltage level of the bit line clamp signal BL_CLMP, minus the threshold voltage Vth of the NMOS transistor N3.

In the second section, the precharge signal PRE_VDAT transitions from the ground voltage GND level to the high voltage VPPSA level. As a result, the PMOS transistor P2 is turned off. In this state, the sensing voltage VDAT is output according to the read voltage Vread_RESET / SET of the global bit line GBL.

8 is another operation timing diagram of the sensing current voltage converter 200 according to the present invention.

Referring to FIG. 8, the operation in the other section is the same as the above embodiment, and only the timing operation in the read mode section t3 is different. That is, in this embodiment, the bit line clamp signal BL_CLMP is kept constant at the overdrive voltage VCLMP_H level in the first section, and then gradually decreases (continuously) in the second section to become the normal voltage VCLMP_L level. Even in this case, the read voltage Vread_RESET / SET of the global bit line GBL appears as in the above embodiment.

In the precharge period t4, the word line WL, the precharge signal PRE_VDAT, the bit line clamp signal BL_CLMP, the precharge signal PRE_CLMP, and the global bit line GBL maintain the ground voltage GND level.

9 is a graph illustrating a method of sensing reset data and set data according to the present invention. Referring to FIG. 9, when the sensing voltage VDAT is higher than the reference voltage VREF, the sensor may sense “reset data”. When the sensing voltage VDAT is lower than the reference voltage VREF, the sensor may sense “set data”.

10 is a graph showing a characteristic that the sensing voltage VDAT margin is improved when an overdrive voltage is applied according to the present invention. Referring to FIG. 10, it can be seen that as the VPPSA voltage level increases, the margin between the sensing voltage VDAT in the case of a reset and the sensing voltage VDAT in the case of a set increases.

Therefore, the phase change memory device of the present invention can improve the sensing voltage margin in the case of reset and set by driving the voltage level of the bit line clamp signal BL_CLMP in the read mode to the overdrive voltage VCLMP_H level. As a result, the sensing voltage in the case of reset and the sensing voltage in the case of a set can be easily distinguished based on the reference voltage VREF.

1A and 1B show a conventional phase change resistance element.

2A and 2B show the principle of a conventional phase change resistance element.

3 illustrates the principle of write operation of a conventional phase change resistance cell.

4 is a circuit diagram of a cell array and a column switching unit of a phase change memory device according to the present invention.

5 is a block diagram illustrating a phase change memory device according to the present invention.

6 is a detailed circuit diagram of a sensing current voltage converter according to the present invention.

7 is an operation timing diagram of a sensing current voltage converter according to the present invention.

8 is another operation timing diagram of a sensing current voltage converter according to the present invention.

9 is a graph illustrating a method of sensing reset data and set data according to the present invention.

10 is a graph showing a characteristic that a sensing voltage margin is improved when an overdrive voltage is applied according to the present invention.

Claims (16)

A cell array including a phase change resistance element and configured to read / write data; A sensing voltage adjusting unit configured to output a bit line clamp signal at an overdrive voltage level in a first section of the read mode; And And a sense amplifier configured to compare and amplify a sensing voltage and a reference voltage applied from the cell array, and to control a range of sensing voltage levels according to the bit line clamp signal. The method according to claim 1, The sensing voltage adjusting unit And outputting the bit line clamp signal at a normal voltage level lower than the overdrive voltage level in a second section after the first section of the read mode. The method according to claim 2, The sensing voltage adjusting unit And cause the bit line clamp signal to drop discretely from the overdrive voltage level to the normal voltage level. The method according to claim 2, The sensing voltage adjusting unit And cause the bit line clamp signal to continuously drop from the overdrive voltage level to the normal voltage level. The method according to claim 1, And a write driver configured to supply a driving voltage corresponding to write data to the cell array. The method according to claim 5, And a main reference voltage supply unit configured to supply the reference voltage to the sense amplifier. The method according to claim 1, And the bit line clamp signal is commonly applied to a plurality of sense amplifiers. The method according to claim 1, The sense amplifier A sensing current voltage converter converting a sensing current applied from the cell array into the sensing voltage and controlling the sensing voltage to be constant according to the bit line clamp signal; And And an amplifier for comparing and amplifying the sensing voltage and the reference voltage. The method according to claim 8, The sensing current voltage converter A precharge unit configured to precharge the sensing voltage to a high voltage according to a first precharge signal; A sensing current supply adjusting unit converting the sensing current into the sensing voltage according to the bit line clamp signal; A clamp voltage adjuster configured to adjust a clamp voltage of a global bit line according to the bit line clamp signal; A clamp voltage precharge unit configured to precharge the global bit line to a level of a power supply voltage according to a second precharge signal; And And a clamp voltage precharge control unit configured to selectively supply the power supply voltage to the clamp voltage precharge unit according to the bit line clamp signal. The method according to claim 9, The sensing current voltage converter And the precharge unit and the clamp voltage precharge controller operate to precharge the sensing voltage to the high voltage level during a precharge operation. The method according to claim 9, The sensing current voltage converter And the clamp voltage precharge unit operates to increase the voltage level of the global bit line primarily in a read mode operation. The method according to claim 11, The sensing current voltage converter And the clamp voltage adjuster operates to increase the global bit line voltage level secondly during the read mode operation. The method according to claim 9, The sensing current voltage converter And controlling the sensing voltage by adjusting an amount of the sensing current flowing in the sensing current supply adjusting unit while the clamp voltage adjusting unit is turned on. The method according to claim 13, And when the voltage level of the bit line clamp signal decreases, the level of the sensing current increases. The method according to claim 13, The reset read voltage of the global bit line is a voltage level equal to the overdrive voltage level minus the threshold voltage of the MOS transistor included in the sensing current supply adjuster. The method according to claim 13, And a set read voltage of the global bit line is a voltage level equal to a normal voltage level minus a threshold voltage of a MOS transistor included in the sensing current supply adjuster.

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