JP2003217289A - Read method for semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a read method for a semiconductor device in which defective read can be reduced by suppressing influence of coupling noise in read operation to be performed dividing into two phases, and to provide a semiconductor device. <P>SOLUTION: In a flash memory, at read operation of data from an arbitrary memory cell in a memory mat, a bit line BL alternately has a phase 0 and a phase 1. When first, in read of the phase 0, data of the memory cell connected to odd numbered bit lines BL1, BL3, BL5,... are read out, next, in read of the phase 1, data of the memory cell connected to even numbered bit lines BL2, BL4,... are read out, reset sequence of a sense amplifier SA is introduced, and potential in the sense amplifier SA of the phase 1 is fixed to a reference potential (ground potential) at read of the phase 0. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device read technique, and more particularly to a technique effectively applied to a nonvolatile semiconductor device such as a flash memory which performs a read operation in two phases.

[0002]

2. Description of the Related Art According to a study made by the present inventor, a flash memory as an example of a semiconductor device is
The following technologies are possible.

For example, in a flash memory, a nonvolatile memory element having a control gate and a floating gate is used for a memory cell, and one transistor can constitute the memory cell. The memory cells are connected to the corresponding one word line and one bit line, respectively. A memory array is composed of such a plurality of word lines, a plurality of bit lines, and a plurality of memory cells.

In such a flash memory,
During a read operation from any memory cell in the memory array, the bit lines alternate between phase 0 and phase 1,
In order to avoid coupling between adjacent bit lines, reading is divided into phases 0 and 1. For example, the reading method up to 256 Mbit is not limited to this.
Although the data in the sense amplifier is fixed, the data in phase 1 is not fixed at the time of reading in phase 0 and is in a floating state.

As a technique relating to a non-volatile semiconductor device such as a flash memory as described above, see, for example, "Advanced Electronics I-9 VLSI LSI Memory" P23 to P28 issued by Baifukan Co., Ltd. on November 5, 1994. The described technology may be mentioned.

[0006]

By the way, as a result of the present inventor's examination of the above-mentioned flash memory reading technique, the following facts have become clear.

For example, in the read operation of the flash memory as described above, the phase 1 bit line in the floating state may be coupled by the adjacent phase 0 bit line. Therefore, for example, as shown in FIG.
L1, BL3, BL5, ... Receive coupling noise from the bit lines BL2, BL4 ,.
5, ... is raised. This is considered to lead to inversion of data because the capacitance increases and the coupling noise increases when the wiring pitch becomes narrow.

Therefore, the present inventor has come up with the idea of resetting a different phase when reading a certain phase as a countermeasure against the coupling noise received via the different phase bit line in the sense amplifier. This is not particularly limited, but it is considered that, for example, in 512 Mbit, the bit wiring pitch becomes narrower than in 256 Mbit, and in the future, as the wiring becomes finer, the cup to be received from the different phase will be used. Canceling the influence of ring noise is considered to be an important technique.

Therefore, an object of the present invention is to provide a reading method for a semiconductor device such as a flash memory which can reduce the read failure by suppressing the influence of coupling noise in the read operation performed in two phases. And to provide a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a method of reading a semiconductor device according to the present invention includes a plurality of word lines, a plurality of bit lines, a corresponding one word line and a plurality of memory cells connected to the one bit line. A memory array including
It has a plurality of sense amplifiers for detecting and amplifying the data read from any memory cell in this memory array,
The read operation from the memory cell is divided into two phases, and the inside of the sense amplifier in the second phase is reset when the first phase is read.

Further, in the method of reading the semiconductor device, during the read operation from the memory cell, the bit line of the second phase is set to the reference potential before the read data is transferred from the memory cell to the sense amplifier. Is. Further, the sense amplifier is connected to the first bit line and the second bit line that form a pair, and when reading from the memory cell connected to the first bit line, the sense amplifier is connected to the memory cell connected to the second bit line. It was designed to be charged. In particular, the memory cell is applied to a nonvolatile memory element having a control gate and a floating gate.

The semiconductor device according to the present invention also includes a memory including a plurality of word lines, a plurality of bit lines, and a corresponding one word line and a plurality of memory cells connected to the one bit line. The array, a plurality of sense amplifiers for detecting and amplifying the data read from any memory cell in this memory array, and the read operation from the memory cell are performed in two phases, and the second phase is used when the first phase is read. And a sense amplifier resetting means for resetting the inside of the sense amplifier.

Therefore, the reading method of the semiconductor device,
Further, according to the semiconductor device, it is possible to reduce read failures, and as a result, it is possible to improve reliability. That is, since the different phase in the sense amplifier is reset and fixed to the reference potential during reading, the coupling noise of the same phase received through the different phase is reduced. Therefore, conventionally, even when the signal amount is reduced and the data is inverted in the sense amplifier, the noise is reduced and the data is less likely to be inverted.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration diagram showing a memory array in a semiconductor device according to an embodiment of the present invention,
2 is a layout diagram in the memory array for explaining the read operation performed in two phases, FIG. 3 is an explanatory view showing the read operation introducing a reset sequence, FIG. 4 is a circuit diagram showing the periphery of the sense amplifier, and FIG. 5 is a timing chart showing a read sequence.

First, an example of the structure of the memory array in the semiconductor device of this embodiment will be described with reference to FIG.

The semiconductor device according to the present embodiment is not particularly limited, but is, for example, a flash memory, and the memory array is divided into upper and lower parts (bit line direction) and left and right parts (word line direction). And four memory mats MMUL / R and MMDL / R, and a plurality of sense amplifiers SA arranged on the center side between the upper and lower memory mats.
L / R and a plurality of data latches DLUL / R and DLDL / R arranged outside the upper and lower memory mats, respectively.
And sub-decoders SDC / L / R respectively arranged on the center side and the outside sandwiched between the left and right memory mats, and a main decoder MD arranged on the outside of the left sub-decoder. Although not shown, a flash memory is further configured by including an indirect system circuit such as a control circuit and a power supply circuit, and the circuit elements configuring each of these circuits are made of monocrystalline silicon such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. It is formed on each semiconductor substrate.

Memory mats MMUL / R, MMDL / R
Is composed of a plurality of word lines WL, a plurality of bit lines BL, a corresponding one word line WL and a plurality of memory cells MC connected to one bit line BL, and the like. The memory cell MC is composed of a nonvolatile memory element having a control gate and a floating gate.

In FIG. 1, a plurality of memory cells M arranged in parallel are provided.
A plurality of memory cell columns of C are arranged in the word line direction and the bit line direction, respectively. In each memory cell column, the drains of a plurality of memory cells MC are connected in common, connected to the bit line BL via the selection MOS transistor QD driven by the selection signal line SiD, and the sources are connected in common and selected. It is connected to the ground potential via the selection MOS transistor QS driven by the signal line SiS.

The sense amplifier SAL / R detects the level of the bit line BL at the time of reading and gives a potential according to the write data at the time of writing. The data latches DLUL / R and DLDL / R hold write data and read data. In addition, each memory mat MM
The word line WL connected to an arbitrary memory cell MC in the UL / R and MMDL / R is a sub-decoder SDC / L / R.
And selected according to the decoding result of the main decoder MD.

Next, referring to FIGS. 2 and 3, an example of a read operation performed in two phases in the flash memory of the present embodiment will be described.

In the flash memory, the bit lines BL are alternately set to phase 0 and phase 1 in order to avoid coupling between adjacent bit lines during a data read operation from any memory cell MC in the memory mat MM. Reading is divided into phases 0 and 1.

For example, as shown in FIG. 2, in the reading order, first, in the reading of the phase 0, the data of the memory cells MC connected to the odd-numbered bit lines BL1, BL3, BL5, ... Is read. Next, in the reading of phase 1, even-numbered bit lines BL2, B
The data of the memory cell MC connected to L4, ... Is read.

At this time, the coupling capacitance is usually large between the bit line BL1 and the bit line BL2, and is small between the bit line BL1 and the bit line BL3. Further, at the time of reading in phase 1, although the data in the sense amplifier SA of phase 0 is fixed,
When reading, the data of Phase 1 has not been finalized,
It is in a floating state. The phase 1 bit line BL in the floating state is connected to the adjacent phase 0.
Since the bit line BL may receive coupling, the present embodiment takes measures as shown in FIG.

That is, as shown in FIG. 3, the reset sequence of the sense amplifier SA is introduced during the read operation, the sense amplifier SA of the phase 1 is fixed to the reference potential (ground potential) during the read of the phase 0, and the phase 0 is read. The method of reducing the coupling noise to is adopted.

Next, referring to FIGS. 4 and 5, an example of a read sequence performed in two phases will be described in detail. The read sequence performed in two phases and the sense amplifier reset sequence are controlled by the control circuit in the indirect circuit.

As shown in FIG. 4A, the sense amplifier S
A is connected by being sandwiched between a pair of bit line BLD and bit line BLU, and precharges the memory cell MC connected to the bit line BLU at the time of reading from the memory cell MC connected to the bit line BLD. Conversely, at the time of reading from the memory cell MC connected to the bit line BLU, it operates so as to precharge the memory cell MC connected to the bit line BLD. In addition, each bit line BL
D and BLU are connected to data latches DLD and DLU, respectively, on the side opposite to the sense amplifier SA.

Specifically, the circuit configuration of the sense amplifier SA and the upper side (MMU) of the memory mat MM will be described with reference to FIG. The sense amplifier SA is a bit line BLU,
It is connected between signal lines SLU and SLD connected to BLD, and it has two PMOS transistors Q1 and Q2 and two Ns.
It has a CMOS type latch type (gate-drain crossing type) circuit type composed of MOS transistors Q3 and Q4, and the PMOS transistors Q1 and Q2 are signal lines SL.
The P and NMOS transistors Q3 and Q4 are connected to the signal line SLN, respectively. A sense amplifier reset circuit, a data transfer circuit, and a precharge circuit are connected between the sense amplifier SA and the memory cell MC.

The sense amplifier reset circuit is a circuit for resetting the sense amplifier SA, is connected to the signal line SLU, and is connected to the sense amplifier reset signal line R.
It is composed of an NMOS transistor Q5 driven by SA.

The data transfer circuit is a circuit for transferring read data from the memory cell MC to the sense amplifier SA, is connected between the signal line SLU and the bit line BLU, and is an NMOS transistor driven by the signal line TR. Q6, an NMOS transistor Q7 connected to both ends of the NMOS transistor Q6 and driven by the signal line PC, and an NMOS transistor Q connected to the signal line FPC.
It is composed of 8.

The precharge circuit is a circuit for precharging the memory cell MC on the dummy side, is connected to the bit line BLU, and is driven by the signal line RPC.
It is composed of an OS transistor Q9.

Sense amplifier SA configured as described above
And the peripheral circuits thereof, a read sequence divided into two phases is executed as shown in FIG. In addition,
In FIG. 5, U and D at the end of each signal line are memory mats M
The upper side (MMU) and the lower side (MMD) of M are shown, and the numbers in [0] and [1] show the phase.

At the time of reading in phase 0, the signal line SL
After displacing D / U from VSS to VRD2 and VSS, the memory mat MMU is set to VBCUT-Vth and the memory mat MMD is set to VSS. At this time, the bit line BL
D becomes VSS after being displaced from VSS to VRD2,
Further, the bit line BLU is changed from VSS to VRD1L, and then is compared with “0” or “1”, and then VSS
Becomes The signal line SLP / N is synchronized with the signal line SLD / U and, after being displaced from VSS to VRD2, the memory mat MMU is VBCUT-Vth and the memory mat MMD is V.
Set to SS. The signal line RPCD is displaced from VSS to VRD2 in synchronism with the bit line BLD, and then becomes VSS. The signal line RPCU is synchronized with the bit line BLU, and VS
Displace from S to VRD1L, VSS, VRD1L, and then to VSS.

The signal line TR is the signal line SLD / U.
, VBCUT-Vth (memory mat MMU), VS
In synchronization with the displacement to S (memory mat MMD), VSS
To VRT, then VSS. Signal line R
The SAD / U causes the signal line TR to be displaced from VSS to VCC before being displaced from VSS to VRT, and then to VSS. At this time, in the phase 1 sense amplifier SA, the phase 0 signal line RSAD / U is normally VCC.
Although it is in the VSS state when it is displaced to, the signal line RSAD / U of the phase 1 is displaced to VCC as indicated by the broken line in this embodiment, and the VCC is maintained until the subsequent reading of phase 1. Sequence control.

As described above, in the reading sequence, the signal line RS of the phase 1 is read at the time of reading the phase 0.
By changing the section where AD / U [1] = “L” is set to “H” and resetting the sense amplifier SA, the sense amplifier SA is fixed to VSS and coupling noise to phase 0 is reduced. It can be reduced.

At the time of reading in phase 1, reading is performed at the same timing as in phase 0 after the reading operation in phase 0 described above. However, when reading in phase 1, the sense amplifier SA in phase 0
Since the data inside is fixed, sequence control such as the read operation of phase 0 is unnecessary.

Therefore, according to the present embodiment, in the read operation performed in two phases, the different phase in the sense amplifier SA is reset at the time of reading and is fixed to the reference potential, so that it is received through the different phase. Since the coupling noise in the same phase is reduced, even if the data amount in the sense amplifier SA is inverted due to the decrease in the signal amount, the noise is reduced and the data inversion is less likely to occur, thus reducing the read failure. be able to.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the case where the present invention is applied to the flash memory has been described, but the present invention is not limited to this, and is applicable to other non-volatile memories and memories in general, and memory / logic mixed semiconductor devices. The present invention can be widely applied, and in particular, can be favorably applied to a semiconductor memory device in which wiring is becoming finer.

[0041]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) In the read operation performed by dividing into two phases, when the read operation of a certain phase is performed, the read method of resetting the sense amplifier of the different phase and fixing it to the reference potential is adopted. It is possible to reduce the coupling noise received through the connection.

(2) According to the above (1), since the data inversion does not easily occur due to the influence of the coupling noise being suppressed, the read failure can be reduced, and as a result, the reliability can be improved. It is possible to provide a method of reading a semiconductor device such as a flash memory and a semiconductor device which can be performed.

[Brief description of drawings]

FIG. 1 shows a semiconductor device according to an embodiment of the present invention,
It is a block diagram which shows a memory array.

FIG. 2 shows a semiconductor device according to an embodiment of the present invention,
FIG. 7 is a layout diagram in the memory array for explaining a read operation performed in two phases.

FIG. 3 shows a semiconductor device according to an embodiment of the present invention,
It is explanatory drawing which shows the read-out operation which introduced the reset sequence.

FIG. 4A and FIG. 4B are circuit diagrams showing the periphery of a sense amplifier in the semiconductor device of one embodiment of the present invention.

FIG. 5 shows a semiconductor device according to an embodiment of the present invention,
It is a timing diagram which shows a read sequence.

FIG. 6 is an explanatory diagram showing a read operation in the semiconductor device examined as the premise of the present invention.

[Explanation of symbols]

MMUL / R, MMDL / R memory mat SAL / R sense amplifier DLUL / R, DLDL / R data latch SDC / L / R sub-decoder MD main decoder WL word line BL bit line MC memory cell QD, QS selection MOS transistor Q1, Q2 PMOS transistor Q3-Q9 NMOS transistor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/792 G11C 17/00 634B F term (reference) 5B025 AD05 AD11 AE00 5F083 EP02 EP22 EP32 EP77 ER22 GA12 LA03 LA09 LA13 LA30 5F101 BA01 BB02 BD02 BD33 BE02 BF08

Claims (5)

[Claims] 1. A plurality of word lines, a plurality of bit lines,
A memory array including a plurality of memory cells connected to corresponding one word line and one bit line, and a plurality of senses for detecting and amplifying data read from any memory cell in the memory array. A read operation from the memory cell is divided into two phases, and the sense amplifier in the second phase is reset when the first phase is read. 2. The method of reading a semiconductor device according to claim 1, wherein during a read operation from the memory cell, the bit line of the second phase is set before the read data is transferred from the memory cell to the sense amplifier. A method for reading a semiconductor device, which comprises setting a reference potential. 3. The method of reading a semiconductor device according to claim 1, wherein the sense amplifier is connected to a pair of first bit line and second bit line, and is connected to the first bit line. The method for reading a semiconductor device is characterized in that the memory cell connected to the second bit line is precharged at the time of reading from. 4. The method of reading a semiconductor device according to claim 1, wherein the memory cell is a nonvolatile memory element having a control gate and a floating gate. 5. A plurality of word lines and a plurality of bit lines,
A memory array including a plurality of memory cells connected to corresponding one word line and one bit line, and a plurality of senses for detecting and amplifying data read from any memory cell in the memory array. A semiconductor device comprising: an amplifier; and a sense amplifier reset means for performing a read operation from the memory cell in two phases and resetting the sense amplifier in the second phase at the time of read in the first phase.