KR101224259B1 - High speed sense amplifier and Method of operating the high speed sense amplifier - Google Patents
High speed sense amplifier and Method of operating the high speed sense amplifier Download PDFInfo
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- KR101224259B1 KR101224259B1 KR1020100138557A KR20100138557A KR101224259B1 KR 101224259 B1 KR101224259 B1 KR 101224259B1 KR 1020100138557 A KR1020100138557 A KR 1020100138557A KR 20100138557 A KR20100138557 A KR 20100138557A KR 101224259 B1 KR101224259 B1 KR 101224259B1
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- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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Abstract
A sense amplifier of a semiconductor memory device having a memory cell array having a plurality of memory cells includes a sense amplifier circuit for sensing and amplifying a difference between a cell current of a first input node and a reference current of a second input node, and the sense amplifier circuit. A current coupled to the first and second input nodes of to provide a multiple of N times the bias current to the first and second input nodes, where N is two or more natural number-amplified first and second distributed currents, respectively. It includes a mirror circuit. A simple current mirror structure provides a fast response speed of the sense amplifier and provides high sensitivity during read operation of the sense amplifier by separating the bit line node and the input of the sense amplifier. .
Description
The present invention relates to a sense amplifier of a semiconductor memory.
Spin-Transfer-Torque MRAM (hereinafter STT-MRAM) is being actively researched as the next generation universal memory. Universal memory features nonvolatile and infinite write cycles. Such a universal memory is expected to bring a significant performance improvement in digital devices because it can store information even when the power is turned off when the fast operation speed is high.
However, the limitations of silicon-based memory and the development of conventional DRAM, SRAM, and flash memory have their advantages and disadvantages due to their inherent limitations. On the other hand, STT-MRAM, a magnetic-based memory using spin torque, is being researched rapidly as a powerful next-generation memory that can replace existing memory due to its high density, high speed, and non-volatile advantages.
STT-MRAM is based on MTJ (Magnetic Tunnel Junction), which is composed of a free layer, a tunnel barrier, and a pinned layer. MTJ, a cell of MRAM composed of a ferromagnetic layer, has the following characteristics.
Firstly, MTJ is nonvolatile due to memory operation along the magnetization direction. Secondly, the MTJ has a low power and high integration due to the decrease in critical current density as the device size decreases. Thirdly, the MTJ has a faster switching speed in the magnetization direction due to spin torque, which allows a write operation faster than a DRAM in theory.
These advantages make STT-MRAM a new next-generation memory. However, the method for driving STT-MRAM requires precise current and voltage control to guarantee the data of the MTJ cell, and the need to improve the read and write speed in terms of circuitry for faster speed than DRAM. have.
Another important feature of STT-MRAM is the rate of change of magnetoresistance (MR) relative to the MTJ voltage. MR decreases as the voltage applied to the MTJ increases. Therefore, precise voltage and current control is required to ensure sufficient sensing margin during read operation.
1 is a conceptual diagram of a sense amplifier used in a conventional voltage-type MRAM. The cell structure of FIG. 1 is a basic 1T 1MTJ structure. That is, the cell on the left consists of one transistor M01 and one MTJ (MTJ1), and the reference cell on the right consists of one transistor M02 and one MTJ (MTJ2). MTJ1 10 and MTJ2 30 may each be modeled as a resistor.
On the other hand, a current method that receives the input of the
In the case of the conventional voltage method, the response speed is slower than that of the current method, but the voltage of the V BL node (bit line node voltage) is applied to the input node of the sense amplifier 200-the gate node of the
As the density of memory cells increases, the read current decreases in proportion, so the read current must be very low, such as several amperes.
Therefore, in the current method, since the input current is small, compensation for sensing margin and response speed of the sense amplifier is necessary. In addition, in the conventional current method, since the gain of the sense amplifier is very large, kickback noise may occur when the output of the sense amplifier affects the bit line node during operation, and thus sensitivity during read operation. There is a problem that fall.
When the voltage method is used so that there is no interference to the cell of the MTJ due to the kickback noise during the read operation, the response speed during the read operation is lower than that of the current method. In the case of the current method, the response speed during the read operation is determined by the voltage method. Higher than this, but the interference of the MTJ cell due to the kickback noise occurs, the sensitivity (sensitivity) is reduced during the read operation.
Accordingly, an object of the present invention is to provide a sense amplifier for improving response speed during a read operation while having high sensitivity in read operation in consideration of an operation characteristic of the MRAM.
The sense amplifier of the semiconductor memory device having a memory cell array having a plurality of memory cells according to an aspect of the present invention for achieving the above object of the present invention is the reference of the cell current of the first input node and the reference of the second input node A sense amplifier circuit that senses and amplifies the difference between the currents and a bias current coupled to the first and second input nodes of the sense amplifier circuit to the first and second input nodes by N times where N is a natural number greater than two A current mirror circuit providing the amplified first and second distributed currents respectively.
In addition, a semiconductor memory device having a memory cell array having a plurality of memory cells according to another aspect of the present invention for achieving the object of the present invention is included in the cell current of the first input node and the reference current of the second input node A method of operating a sense amplifier that senses and amplifies a difference between the steps of receiving a bias current and N times the bias current to the first and second input nodes of the sense amplifier circuit, where N is a natural number of two or more Providing a first distribution current and a second distribution current, respectively, and distributing the N times amplified first and second distribution currents when the sense amplifier enable signal is activated to respectively divide the first and second distribution currents of the sense amplifier circuit. Providing as a cell current and a reference current to a second input node.
As described above, according to the sense amplifier according to the embodiments of the present invention, a simple current mirror structure may be used to compensate for a low sensing margin due to a very low input current in the conventional current method. In addition, by ensuring sufficient sensing margin, it is possible to realize faster response speed than conventional current methods.
In addition, by separating the bit-line node and the sense amplifier input stage, it is possible to prevent kickback noise generated by the existing current method, so that it has a high sensitivity during read operation. Read operation can be performed.
In particular, when applied to STT-MRAM, the next-generation memory using magnetoresistance, it can perform fast and stable operation even at low Tunneling Magnetoresistance (TMR), and it will be able to show sufficient performance even if the cell performance of STT-MRAM is not high. In addition, the cost can be reduced due to the simple structure and simple operation method, and thus high efficiency can be achieved.
1 is a conceptual diagram of a sense amplifier used in a conventional voltage-type MRAM.
2 is a conceptual diagram illustrating a sense amplifier according to an embodiment of the present invention.
FIG. 3 shows a detailed circuit diagram of the sense amplifier circuit of FIG. 2.
4 is an operation timing diagram of a sense amplifier according to an embodiment of the present invention.
5 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the amplification factor of a current mirror.
6 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the TMR.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.
When a component is referred to as being "top" or "bottom" of another component, it should be understood that other components may be present in between, although they may be formed directly on the other component.
The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.
When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.
Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate a thorough understanding of the present invention, the same reference numerals are used for the same means regardless of the number of the drawings.
First, the overall operation of the bit line sense amplifier will be described.
Although not shown in the drawings, the semiconductor memory includes a memory cell array having a plurality of memory cells, each of which is connected to a word line WL and a bit line and is connected to the bit line BL by a bit line sense amplifier. The carried amplified data is transferred to the data bus to read the data.
The bit line BL is precharged to a precharge voltage, for example, 1/2 of the internal power supply voltage VDD, wherein the bit line BL and the bit line BLB to which the selected memory cell is connected are not. The two bit lines BL are equalized to eliminate the voltage difference between them. The row decoder analyzes an externally input row address to select a word line WL corresponding to the row address, and the bit line BL connected to the memory cell connected to the selected word line WL and the bit line BL not connected to the row line. A potential difference is generated between the BLBs.
In this case, when the sense amplifier control signal Ven is enabled, the sense amplifier operates to sense and amplify a potential difference between the bit line BL to which the selected memory cell is connected and the bit line BLB to which the selected memory cell is not connected. For example, assuming that the data stored in the selected memory cell is low-level data, the voltage of the bit line BL to which the selected memory cell is connected is lower than the precharge voltage. In this case, the bit line to which the selected memory cell is not connected Since the voltage of the BLB maintains the precharge voltage, a potential difference occurs between the two bit lines BL and BLB.
Subsequently, when the column address is analyzed by the column decoder and the column control signal corresponding to the column address is enabled, the amplified data carried on the bit line BL is transmitted to the data bus by the bit line sense amplifier.
Hereinafter, a sense amplifier according to an embodiment of the present invention will be described.
2 is a conceptual diagram illustrating a sense amplifier according to an embodiment of the present invention, FIG. 3 is a detailed circuit diagram of the sense amplifier circuit of FIG. 2, and FIG. 4 is an operation timing diagram of the sense amplifier according to an embodiment of the present invention. to be.
Referring to FIG. 2, the memory cell Cell connected to the selected word line WL includes
The reference cell includes MTJ2 310, which is modeled as a resistor, and M02 having a word line WL connected to a gate thereof. Bit line BLB is V BLB of reference cell Is connected to the voltage node.
2, a sense amplifier according to an embodiment of the present invention includes a
The
The current source I bias is MTJ1 (110) and MTJ2 second reference to provide a first reference current I ref1 to MTJ1 (110) to divide the current of current source I bias, and MTJ2 310 to now applying a bias to the 310 Provide the current I ref2 .
The first
The second
The sense amplifier according to an embodiment of the present invention compensates for the low sensing margin due to the very low input current of the
In addition, the sense amplifier according to an embodiment of the present invention provides a structure in which a bit line BL node connected to a memory cell and a first input node (node c of FIG. 3) of the sense amplifier are separated. In addition, a bit line (BLB) node connected to a reference cell corresponding to the memory cell and a second input node (node d) of the sense amplifier are provided. Specifically, V BL determined by the state of the memory cell to the gates of MP01 and MP02 of the
Therefore, due to the large gain of the
Hereinafter, an operation of a sense amplifier according to an embodiment of the present invention will be described with reference to FIG. 3.
Referring to FIG. 3, a sense amplifier according to an embodiment of the present invention includes a cell
The cell
The first
The second
When the sense amplifier enable signal V EN becomes High, the first input
When the sense amplifier enable signal V EN becomes High, the second input
The
The
When the sense amplifier enable signal V EN becomes High, the current amplified in the ratio of 1: N by the
The
The
Hereinafter, the operating mechanism of the sense amplifier according to the exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4.
In the sense amplifier according to the exemplary embodiment of the present invention, first, both ends of the output nodes a and b of the sense amplifier are precharged so that the bit line BL is precharged, for example, 1 / time of the internal power supply voltage VDD. It is pre-charged to 2- and the two bit lines BL and BLB are equalized. Specifically, when the row decoder analyzes an externally input row address and selects a word line WL corresponding to the row address, the word line selection signal V WL is activated at high at T1 to be coupled to the word line WL. At the same time as M01 is selected, a cell is loaded and both ends (output nodes a and b) of the
When the transistor M01 coupled to the word line WL is turned on and the cell is loaded, the bit line voltages V BL and V BLB are determined according to resistance values of the MTJ1 and MTJ2 (reference cell), and accordingly, a first configured of M01 and M02 The current is amplified by a preset ratio of 1: N in the
Then, when the sense amplifier enable signal V EN signal is activated high to operate the sense amplifier at T2 while the word line select signal V WL is activated high, it is amplified by the
Subsequently, when the column address is analyzed by the column decoder and the column control signal corresponding to the column address is enabled, the amplified data carried on the bit line BL is transmitted to the data bus by the bit line sense amplifier.
Here, the amplification factor of the current mirror is defined by the following simple equations (1) to (3).
[Equation 1]
I dm 01 = -1 / 2 u p c ox (W / L) m 01 (V GS -V TH ) 2
&Quot; (2) "
I dm02 = -1 / 2 u p c ox (W / L) m 01 (V GS -V TH ) 2
&Quot; (3) "
I dm02 = I dm01 [(W / L) 02 / (W / L) 01 ]
(However, PMOS transistors MP01, MP02 and MP04, MP05 are all operative in the saturation region, I dm01 is a drain current in a saturation region of the PMOS transistor MP01, I dm02 is a drain current in a saturation region of the PMOS transistor MP02, u p Is the mobility of holes, c ox is the thickness of oxide used as the insulating film, W is the channel width, L is the channel length, W / L is the aspect ratio, V GS is the voltage difference between gate and source, and V TH is the threshold voltage.
In the same manner as above, the current may be amplified in the ratio of 1: N in the first
If the MTJ has an MR ratio of 100% and the cell current is 5 uA or less, the cell current difference is about 0.1 uA or less. When the current is amplified by about 10 times, the current difference entering the
5 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the amplification factor of a current mirror.
In FIG. 5, when the ratio of Tunneling Magnetoresistance (TMR) is 100% and the current flowing through the MTR is 2 uA, the amplification ratios of the
Referring to FIG. 5, it can be seen that the response speed of the sense amplifier can be improved by adjusting the amplification factor of the current mirror of FIG. 3 according to an embodiment of the present invention. That is, it can be seen that the response speed is improved as the amplification ratio N of the
6 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the TMR.
6 shows the response characteristics of the sense amplifier while changing the TMR to 200%, 100%, 50%, and 10% when the amplification ratio N = 1 of the current mirror and the current flowing through the MTR is 2uA.
Referring to FIG. 6, it can be seen that the larger the TMR, the faster the response speed of the sense amplifier.
In the case of commercially available products, the TMR has a value of 100% or less. Referring to FIGS. 5 and 6, the response speed of the sense amplifier is increased by increasing the amplification ratios N of the
The sense amplifier according to the embodiments of the present invention is not limited to MRAM, but is similarly applied to phase change RAM (PCRAM), which is being actively developed as a next-generation memory, so that the sense amplifier has high sensitivity and improves operation speed during read operation of the sense amplifier. Can be applied. PCRAM is a non-volatile memory that uses heat to change a substance into crystalline or amorphous material. The PCRAM is similar to a sensing method using an MRAM that uses resistivity to classify data into resistance components according to a change in material properties. In addition, the sense amplifier according to the embodiments of the present invention is also applied to ReRAM, which is a next-generation memory device using resistivity, and has high sensitivity during read operation of the sense amplifier and may be applied to improve the operation speed.
Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.
130, 330: current mirror
140, 340: input current distribution circuit
200: sense amplifier circuit
Claims (12)
A sense amplifier circuit for sensing and amplifying a difference between the cell current of the first input node and the reference current of the second input node; And
N times the bias current to the first and second input nodes coupled to the first and second input nodes of the sense amplifier circuit, where N is the two or more natural number-amplified first and second distribution currents. And a current mirror circuit for providing each of the sense amplifiers of the semiconductor memory device.
A first current mirror which amplifies the first reference current divided by the bias current by N times to generate a first divided current and provides the first divided current to the first input node of the sense amplifier circuit; And
And a second current mirror configured to generate a second distribution current by amplifying the second reference current divided by the bias current by N times to generate a second distribution current and to provide the second input node to the sense amplifier circuit. amplifier.
A first PMOS transistor having a source coupled to one end of a current source supplying the bias current, the gate being connected to a drain and a first bit line node; And
A second PMOS transistor having a gate connected to the gate of the first PMOS transistor, a source coupled to one end of a current source supplying the bias current, and a drain connected to the first input node of the sense amplifier circuit
A sense amplifier of a semiconductor memory device comprising a.
A third PMOS transistor having a source coupled to one end of a current source supplying the bias current, the gate being connected to a drain and a second bit line node; And
A fourth PMOS transistor having a gate connected to the gate of the third PMOS transistor, a source coupled to one end of a current source supplying the bias current, and a drain connected to the second input node of the sense amplifier circuit
A sense amplifier of a semiconductor memory device comprising a.
A first input current distribution circuit for distributing the first distribution current amplified N times by the first current mirror to provide a cell current to a first input node of the sense amplifier circuit when the sense amplifier enable signal is activated; And
A second input current distribution circuit for distributing the second distribution current amplified N times by the second current mirror to provide a reference current to the second input node of the sense amplifier circuit when the sense amplifier enable signal is activated
The sense amplifier of the semiconductor memory device further comprises.
A drain of the second PMOS transistor and a first input node of the sense amplifier circuit, a gate of which is connected to a source, and a source of which includes a first NMOS transistor connected to ground Sense amplifiers.
A drain of the fourth PMOS transistor and a second input node of the sense amplifier circuit, a gate of which is connected to a source, and a source of which includes a second NMOS transistor connected to ground Sense amplifiers.
Receiving a bias current; And
Providing a first distribution current and a second distribution current, wherein the bias current is N times the first and second input nodes of the sense amplifier circuit, where N is at least two natural number-amplified first and second distribution currents, respectively; And
Distributing the N and amplified first and second distribution currents when the sense amplifier enable signal is activated and providing them as the cell current and reference current to the first and second input nodes of the sense amplifier circuit, respectively.
Method of operation of a sense amplifier comprising a.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324384B2 (en) | 2014-01-17 | 2016-04-26 | Samsung Electronics Co., Ltd. | Sense amplifiers and memory devices having the same |
US9443586B2 (en) | 2014-04-07 | 2016-09-13 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, memory system including the same and method for driving nonvolatile memory device |
US11443791B2 (en) | 2019-07-22 | 2022-09-13 | Samsung Electronics Co., Ltd. | Magnetic junction memory device and writing method thereof |
US11515357B2 (en) | 2019-07-18 | 2022-11-29 | Samsung Electronics Co., Ltd. | Magnetic junction memory device and reading method thereof |
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KR102020975B1 (en) | 2013-07-30 | 2019-10-18 | 삼성전자주식회사 | Current sense amplifying circuit in semiconductor memory device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020093593A (en) * | 2001-06-07 | 2002-12-16 | 가부시끼가이샤 도시바 | Semiconductor memory device |
KR20080024992A (en) * | 2006-09-14 | 2008-03-19 | 키몬다 노스 아메리카 코포레이션 | Resistive memory having shunted memory cells |
-
2010
- 2010-12-30 KR KR1020100138557A patent/KR101224259B1/en not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020093593A (en) * | 2001-06-07 | 2002-12-16 | 가부시끼가이샤 도시바 | Semiconductor memory device |
KR20080024992A (en) * | 2006-09-14 | 2008-03-19 | 키몬다 노스 아메리카 코포레이션 | Resistive memory having shunted memory cells |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324384B2 (en) | 2014-01-17 | 2016-04-26 | Samsung Electronics Co., Ltd. | Sense amplifiers and memory devices having the same |
US9443586B2 (en) | 2014-04-07 | 2016-09-13 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, memory system including the same and method for driving nonvolatile memory device |
US11515357B2 (en) | 2019-07-18 | 2022-11-29 | Samsung Electronics Co., Ltd. | Magnetic junction memory device and reading method thereof |
US11889703B2 (en) | 2019-07-18 | 2024-01-30 | Samsung Electronics Co., Ltd. | Magnetic junction memory device and reading method thereof |
US11443791B2 (en) | 2019-07-22 | 2022-09-13 | Samsung Electronics Co., Ltd. | Magnetic junction memory device and writing method thereof |
US12014763B2 (en) | 2019-07-22 | 2024-06-18 | Samsung Electronics Co., Ltd. | Magnetic junction memory device and writing method thereof |
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