JP5140855B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a driver that causes a current for writing data to a memory element to flow through a write current line.

  MRAM (Magnetic Random Access Memory) is a general term for a solid-state memory that stores data using the magnetization direction of a ferromagnetic material. In the MRAM, “1” and “0” correspond to whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or antiparallel to a certain reference direction. Further, a GMR element using a giant magnetoresistance effect (Giant Magneto Resistive effect: GMR (Giant Magneto Resistive) effect) and a magnetic tunnel effect (Tunneling Magneto Resistance effect: TMR (Tunneling Magneto) An MTJ (Magnetic Tunneling Junction) element or the like that utilizes the (resistive) effect) is used in the MRAM.

  The MTJ element is composed of a three-layer film of ferromagnetic layer / insulating layer / ferromagnetic layer, and a tunnel current flows through the insulating layer. The resistance value to the tunnel current changes according to the relationship between the magnetization directions of the two ferromagnetic layers.

  Here, as a method of reversing the magnetization direction of the ferromagnetic layer, there is known an external magnetization reversal method in which a current is passed in the vicinity of the memory cell to generate an external magnetic field and the magnetization direction of the ferromagnetic layer is reversed. (For example, refer nonpatent literature 1).

As a method for reversing the magnetization direction of the ferromagnetic layer, a spin injection magnetization reversal method is known (for example, see Non-Patent Document 2). This is a method in which a current is directly applied to a memory cell to reverse the magnetization by the action of electrons' spin (direction). More specifically, this is a method of reversing the magnetization of the ferromagnetic layer by passing a current (hereinafter also referred to as a spin injection current) from one ferromagnetic layer of the TMR element to the other ferromagnetic layer. Since the spin injection current can have a smaller amount of current than the current for generating the external magnetic field, the spin injection magnetization reversal method can reduce the current consumption of the MRAM compared to the external magnetization reversal method.
Takaharu Tsuji et al. "A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture", 2004 Symposium on VLSI Circuits Digest of Technical Papers pp.450-453 M. Hosomi et al. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM", 2005 IEDM 19_1

  By the way, an inspection for detecting a defect of the MRAM from the distribution of the electric resistance value of each MTJ element is performed by measuring the electric resistance value of each MTJ element included in the MRAM from the outside.

  However, in order to perform such an inspection, a test pad for supplying a voltage from the outside to the MTJ element and a connection and a non-connection between the test pad and the MTJ element at the time of inspection and normal time are switched. Switching circuit and a control circuit for controlling the switching circuit are required, which increases the layout area.

  In addition, since the wiring length between the MTJ element and the test pad disposed on the outer peripheral portion of the semiconductor chip is usually long, the parasitic resistance of the wiring is increased. In order to accurately measure the electrical resistance value of the MTJ element, it is necessary to reduce the parasitic resistance of the wiring. However, if the wiring width is increased in order to reduce the parasitic resistance, the layout area increases. In addition, the on-resistance of the transistor constituting the switching circuit needs to be reduced in order to accurately measure the electrical resistance value of the MTJ element, but if the transistor size is increased to reduce the on-resistance of the transistor, The layout area increases.

  However, Non-Patent Documents 1 and 2 do not disclose a configuration for solving such a problem.

  Therefore, an object of the present invention is to provide a semiconductor device capable of accurately measuring the electrical resistance value of a memory element and preventing an increase in layout area.

  In summary, a semiconductor device according to an embodiment of the present invention electrically separates a driver for driving a wiring for supplying a data write current to a memory element from a voltage supply pad of another circuit in the semiconductor device. Connect to voltage supply pad.

  According to the embodiment of the present invention, since the memory element and the electric resistance value measuring pad can be connected by a circuit having a small parasitic resistance, an increase in layout area can be prevented.

  Therefore, the electrical resistance value of the memory element can be accurately measured and an increase in layout area can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a schematic block diagram showing the overall configuration of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 1, semiconductor device 101 is, for example, an MRAM, a control circuit 5 that controls the overall operation of semiconductor device 101 in response to a control signal CMD, and MTJ memory cells MC that are integrated and arranged in a matrix. (Hereinafter also simply referred to as memory cell MC), row selection circuits 20, 21, column decoder 25, read / write control circuits 30, 35, a plurality of word lines WL, and a plurality of digits. A line DL, a plurality of bit lines BL, and a plurality of source lines SL are provided.

  Hereinafter, the rows and columns of the plurality of memory cells MC that are integrated and arranged in a matrix included in the memory array 10 are also referred to as memory cell rows and memory cell columns, respectively.

  The row selection circuits 20 and 21 perform a memory cell row selection operation in the memory array 10 to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 performs a memory cell column selection operation in the memory array 10 to be accessed based on the column address CA included in the address signal ADD.

  The read / write control circuits 30 and 35 are provided on both sides of the memory array 10 and write data to the memory cell MC based on the input data DIN. The read / write control circuits 30 and 35 read data from the memory cell MC and output it as read data DOUT to the outside.

  Word line WL, digit line DL, and source line SL are provided corresponding to the memory cell rows, respectively. Bit line BL is provided corresponding to the memory cell column. FIG. 1 representatively shows one memory cell MC, and shows one word line WL and one digit line DL corresponding to the memory cell row of each memory cell MC. Further, one bit line BL is representatively shown corresponding to the memory cell column of the memory cells MC.

  FIG. 2 is a schematic configuration diagram of the memory array 10 and its peripheral circuits according to the first embodiment of the present invention. In FIG. 2, the vertical direction on the paper corresponds to a memory cell row, and the horizontal direction on the paper corresponds to a memory cell column.

  Referring to FIG. 2, memory array 10 includes memory cells MC integrated and arranged in a matrix.

  In FIG. 2, typically, memory cells MC0 to MC5, bit lines BL0 to BL2 and column select lines CSL0 and CSL1 provided corresponding to the memory cell columns, and words provided corresponding to the memory cell rows, respectively. Lines WL0 to WL3, digit lines DL0 and DL1, and source line SL are shown.

  Memory cells MC0 to MC5 include MTJ elements (magnetoresistive elements) S0 to S5 and cell transistors TRS0 to TRS5, respectively.

  Row selection circuit 20 includes a digit line driver DLDV. Digit line driver DLDV includes N-channel MOS transistors TRD0 and TRD1. Row selection circuit 21 is connected to power supply node VCC to which power supply voltage VCC is supplied. Here, since the N channel MOS transistor has a larger current driving capability per gate width than the P channel MOS transistor, a relatively large amount of current can flow through the digit line DL with a small layout area. However, digit line driver DLDV may include a P channel MOS transistor instead of an N channel MOS transistor.

  The read / write control circuit 30 includes a bit line driver BLDV1. Read / write control circuit 35 includes a bit line driver BLDV2, a data read circuit RDC, and N-channel MOS transistors TRC0 to TRC2. Bit line driver BLDV1 includes P channel MOS transistors TRB0, TRB4, TRB8 and N channel MOS transistors TRB1, TRB5, TRB9. Bit line driver BLDV2 includes P channel MOS transistors TRB2, TRB6, TRB10 and N channel MOS transistors TRB3, TRB7, TRB11.

  Hereinafter, each of MTJ elements S0 to S5 is referred to as MTJ element S, each of cell transistors TRS0 to TRS5 is referred to as cell transistor TRS, each of N channel MOS transistors TRD0 and TRD1 is referred to as N channel MOS transistor TRD, and N channel Each of MOS transistors TRB1, TRB3, TRB5, TRB7, TRB9, TRB11 is referred to as an N channel MOS transistor TRB, and each of P channel MOS transistors TRB0, TRB2, TRB4, TRB6, TRB8, TRB10 is referred to as a P channel MOS transistor TRB, Each of N channel MOS transistors TRC0 to TRC2 may be referred to as N channel MOS transistor TRC.

  Digit lines DL0 and DL1 have a first end connected to power supply node VCC, and a second end. A write current IWDL for writing data to the memory cell MC flows through the digit lines DL0 and DL1 when data is written. Further, the direction of the write current IWDL does not depend on the logical value of the write data.

  In digit line driver DLDV, N-channel MOS transistor TRD0 has a drain connected to the second end of digit line DL0 and a source connected to ground node VSS to which ground voltage VSS is supplied. N-channel MOS transistor TRD1 has a drain connected to the second end of digit line DL1, and a source connected to ground node VSS.

  N-channel MOS transistors TRD0 and TRD1 generate a data write magnetic field that acts on the magnetization of MTJ elements S0 to S5 by flowing write current IWDL through digit lines DL0 and DL1 during data write.

  In bit line driver BLDV1, P channel MOS transistor TRB0 has a source connected to power supply node VDD, a drain connected to bit line BL0, and a gate. N-channel MOS transistor TRB1 has a source connected to ground node VSS, a drain connected to bit line BL0, and a gate. P-channel MOS transistor TRB4 has a source connected to power supply node VDD, a drain connected to bit line BL1, and a gate. N-channel MOS transistor TRB5 has a source connected to ground node VSS, a drain connected to bit line BL1, and a gate. P-channel MOS transistor TRB8 has a source connected to power supply node VDD, a drain connected to bit line BL2, and a gate. N-channel MOS transistor TRB9 has a source connected to ground node VSS, a drain connected to bit line BL2, and a gate.

  In bit line driver BLDV2, P channel MOS transistor TRB2 has a source connected to power supply node VDD, a drain connected to bit line BL0, and a gate. N-channel MOS transistor TRB3 has a source connected to test node TN, a drain connected to bit line BL0, and a gate. P-channel MOS transistor TRB6 has a source connected to power supply node VDD, a drain connected to bit line BL1, and a gate. N-channel MOS transistor TRB7 has a source connected to test node TN, a drain connected to bit line BL1, and a gate. P-channel MOS transistor TRB10 has a source connected to power supply node VDD, a drain connected to bit line BL2, and a gate. N-channel MOS transistor TRB11 has a source connected to test node TN, a drain connected to bit line BL2, and a gate.

  N-channel MOS transistor TRC0 has a drain connected to read line LIO, a source connected to bit line BL0, and a gate connected to column select line CSL0. N-channel MOS transistor TRC1 has a drain connected to read line LIO_B, a source connected to bit line BL1, and a gate connected to column select line CSL0. N-channel MOS transistor TRC2 has a drain connected to read line LIO, a source connected to bit line BL2, and a gate connected to column select line CSL1.

  In memory cell MC0, MTJ element S0 has a first end connected to bit line BL0, and a second end. Cell transistor TRS0 has a gate connected to word line WL0, a drain connected to the second end of MTJ element S0, and a source connected to source line SL. In memory cell MC1, MTJ element S1 has a first end connected to bit line BL0, and a second end. Cell transistor TRS1 has a gate connected to word line WL2, a drain connected to the second end of MTJ element S1, and a source connected to source line SL. In memory cell MC2, MTJ element S2 has a first end connected to bit line BL1, and a second end. Cell transistor TRS2 has a gate connected to word line WL1, a drain connected to the second end of MTJ element S2, and a source connected to source line SL. In memory cell MC3, MTJ element S3 has a first end connected to bit line BL1, and a second end. Cell transistor TRS3 has a gate connected to word line WL3, a drain connected to the second end of MTJ element S3, and a source connected to source line SL. In memory cell MC4, MTJ element S4 has a first end connected to bit line BL2, and a second end. Cell transistor TRS4 has a gate connected to word line WL0, a drain connected to the second end of MTJ element S4, and a source connected to source line SL. In memory cell MC5, MTJ element S5 has a first end connected to bit line BL2, and a second end. Cell transistor TRS5 has a gate connected to word line WL2, a drain connected to the second end of MTJ element S5, and a source connected to source line SL.

  The data read circuit RDC is connected to read lines LIO and LIOB. Source line SL is connected to ground node VSS.

  The MTJ element S changes its electrical resistance value according to the magnetization direction corresponding to the logical value of the stored data.

  FIG. 3 is a diagram showing the connection between the voltage supply pad and the external device when measuring the electrical resistance value of the MTJ element in the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 3, the semiconductor device 101 includes pads PD1 to PD3 arranged on the semiconductor chip CP.

  Pad PD1 is connected to power supply node VCC. The pad PD2 is connected to the ground node VSS. The pad PD3 is connected to the test node TN.

  When measuring the electrical resistance value of the MTJ element, the voltage V1 from the external power source PS is supplied to the pad PD1. Further, the ground voltage VSS is supplied to the pad PD2. Further, the voltage V2 from the test apparatus 201 is supplied to the pad PD3.

  The power supply wiring connected to the source of the N-channel MOS transistor TRB in the bit line driver BLDV2 is different from the power supply wiring connected to the conduction electrodes of the transistors included in other circuits in the semiconductor device 101 such as the digit line driver DLDV. That is, the test node TN is electrically separated from the power supply node connected to other circuits in the semiconductor device 101.

  FIG. 4 is a diagram showing the connection between the voltage supply pad and the external device during normal operation in the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 4, during a normal operation such as data writing and data reading, voltage V1 from external power supply PS is supplied to pad PD1. Further, the ground voltage VSS is supplied to the pad PD2. The pad PD3 is supplied with the ground voltage VSS.

  Next, operations during data writing and data reading in the semiconductor device according to the first embodiment of the present invention will be described.

  Digit line driver DLDV causes write current IWDL to flow through digit lines DL0 and DL1, respectively, based on row address RA included in address signal ADD during data writing.

  More specifically, when data is written, the N-channel MOS transistor TRD corresponding to the selected memory cell row is turned on by receiving a logic high level voltage at the gate, thereby supplying power through the digit line DL corresponding to the selected memory cell row. A write current IWDL flows from the node VCC to the ground node VSS.

  The bit line driver BLDV1 uses the ground voltage VSS supplied from the ground node VSS and the power supply voltage VDD supplied from the power supply node VDD based on the column selection result by the column decoder 25 at the time of data writing to the bit lines BL0 to BL2. A write current IWBL is passed through. In addition, the bit line driver BLDV2 uses the ground voltage VSS supplied from the test node TN and the power supply voltage VDD supplied from the power supply node VDD based on the column selection result by the column decoder 25 at the time of data writing. A write current IWBL is supplied through .about.BL2. That is, the bit line drivers BLDV1 and BLDV2 flow the write current IWBL for writing data to the memory cells MC0 to MC5 through the bit lines BL0 to BL2, and flow the write current IWBL in the direction corresponding to the logical value of the write data.

  More specifically, for example, when the logical value of the write data is “0”, in bit line driver BLDV1, N channel MOS transistor TRB corresponding to the selected memory cell column receives a logic high level voltage at its gate. Turn on. P channel MOS transistor TRB corresponding to the selected memory cell column is turned off when the gate receives a logic high level voltage. In the bit line driver BLDV2, the P-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic low level voltage. In addition, N channel MOS transistor TRB corresponding to the selected memory cell column is turned off in response to a logic low level voltage at its gate. Then, a write current IWBL flows from the bit line driver BLDV2 to the bit line driver BLDV1 through the bit line BL corresponding to the selected memory cell column.

  On the other hand, when the logical value of the write data is “1”, in the bit line driver BLDV1, the P-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic low level voltage. In addition, N channel MOS transistor TRB corresponding to the selected memory cell column is turned off in response to a logic low level voltage at its gate. In the bit line driver BLDV2, the N-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic high level voltage. P channel MOS transistor TRB corresponding to the selected memory cell column is turned off when the gate receives a logic high level voltage. Then, a write current IWBL flows in the direction from the bit line driver BLDV1 to the bit line driver BLDV2 through the bit line BL corresponding to the selected memory cell column.

  In addition, regardless of whether the logical value of the write data is “0” or “1”, the N-channel MOS transistor TRB corresponding to the non-selected memory cell column in the bit line driver BLDV1 applies a logic high level voltage to the gate. Receive and turn on. Further, the P channel MOS transistor TRB corresponding to the non-selected memory cell column is turned off when the gate receives a logic high level voltage. In the bit line driver BLDV2, the P channel MOS transistor TRB corresponding to the non-selected memory cell column receives a logic high level voltage at the gate and is turned off. Further, N channel MOS transistor TRB corresponding to the non-selected memory cell column is turned off in response to a logic low level voltage at its gate.

  The word lines WL0 to WL3 are driven to a logic high level based on the row selection results by the row selection circuits 20 and 21 when reading data. Then, the cell transistor TRS corresponding to the selected memory cell row is turned on when the gate receives a logic high level voltage. The column selection line CSL is driven to a logic high level based on the column selection result by the column decoder 25 when reading data. Then, N channel MOS transistor TRC corresponding to the selected memory cell column is turned on upon receiving a logic high level voltage at its gate. In bit line drivers BLDV1 and BLDV2, N channel MOS transistor TRB corresponding to the selected memory cell column is turned off by receiving a logic low level voltage at the gate, and P channel MOS transistor corresponding to the selected memory cell column The TRB is turned off when the gate receives a logic high level voltage.

  The data read circuit RDC supplies a read current IR to the source line SL via the bit line BL corresponding to the selected memory cell column, the MTJ element S corresponding to the selected memory cell row and the selected memory cell column, and the cell transistor TRS in the on state. Shed. The data read circuit RDC reads data stored in the memory cells MC corresponding to the selected memory cell row and the selected memory cell column based on the amount of the read current IR.

  Next, a method for measuring the electrical resistance value of the MTJ element in the semiconductor device according to the first embodiment of the present invention will be described.

  When measuring the electrical resistance value of the MTJ element, the row selection circuits 20 and 21 and the column decoder 25 select a memory cell row and a memory cell column corresponding to the MTJ element S to be measured.

  In the bit line driver BLDV1, the P channel MOS transistor TRB corresponding to the selected memory cell column receives a logic high level voltage at the gate and is turned off. In addition, N channel MOS transistor TRB corresponding to the selected memory cell column is turned off in response to a logic low level voltage at its gate. In the bit line driver BLDV2, the N-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic high level voltage. P channel MOS transistor TRB corresponding to the selected memory cell column is turned off when the gate receives a logic high level voltage.

  In the bit line driver BLDV1, the N-channel MOS transistor TRB corresponding to the non-selected memory cell column is turned on when the gate receives a logic high level voltage. Further, the P channel MOS transistor TRB corresponding to the non-selected memory cell column is turned off when the gate receives a logic high level voltage. In the bit line driver BLDV2, the P channel MOS transistor TRB corresponding to the non-selected memory cell column receives a logic high level voltage at the gate and is turned off. Further, N channel MOS transistor TRB corresponding to the non-selected memory cell column is turned off in response to a logic low level voltage at its gate.

  Further, the word line WL corresponding to the selected memory cell row is driven to a logic high level by the row selection circuits 20 and 21. Then, the cell transistor TRS corresponding to the selected memory cell row is turned on when the gate receives a logic high level voltage.

  Then, the MTJ element S to be measured is electrically connected to the pad PD3 via the N channel MOS transistor TRB corresponding to the selected memory cell column in the bit line driver BLDV2.

  The column selection lines CSL0 and CSL1 are driven to a logic low level by the column decoder 25. N-channel MOS transistors TRC0 to TRC2 receive a logic low level voltage at their gates and are turned off.

  N channel MOS transistor TRD corresponding to the selected memory cell row and the non-selected memory cell row is turned off when the gate receives a logic low level voltage. That is, the write current IWDL does not flow when measuring the electrical resistance value of the MTJ element.

  When a voltage is supplied from the test apparatus 201 via the pad PD3, a current flows from the test apparatus 201 to the ground node VSS via the N-channel MOS transistor TRB corresponding to the selected memory cell column and the MTJ element S to be measured. By measuring this current value, the electrical resistance value of the MTJ element S to be measured can be obtained.

  However, the conventional MRAM has a problem in that the layout area increases because the electrical resistance value of each MTJ element included in the MRAM is measured from the outside.

  However, in the semiconductor device according to the first embodiment of the present invention, when the electrical resistance value of the MTJ element S is measured from the outside, the wiring for passing a data write current to the MTJ element S, that is, the bit line BL and the source line SL For the test, the source of the transistor in the bit line driver BLDV2 that directly drives etc. is electrically separated from the external power supply pads PD1 and PD2 connected to other circuits such as the bit line driver BLDV1 and the digit line driver DLDV. To the pad PD3.

  Here, in the bit line driver BLDV, it is necessary to pass a relatively large current of several milliamperes in order to perform a data write operation. Therefore, in the bit line driver BLDV, the transistor size is set larger than that of the data reading circuit such as the transistor TRC, and the width of the power supply wiring is set wider. That is, since the MTJ element S can be connected to the electric resistance value measuring pad by a circuit having a relatively small parasitic resistance, the electric resistance value can be accurately obtained even with a low resistance MTJ element without increasing the layout area. Can be measured. Here, since the demand for reducing the parasitic resistance is increasing due to the high performance, that is, the low resistance of the MTJ element, the effect of the present invention that can accurately measure the electric resistance value of the low resistance MTJ element is great.

  Further, in order to measure the electrical resistance value of the MTJ element, it is only necessary to control on / off of the transistors necessary for normal operation of the semiconductor device. That is, a switching circuit for switching between connection and non-connection of the test pad and the MTJ element and a control circuit for controlling the switching circuit at the time of inspection and normal time are not required, thereby preventing an increase in layout area. be able to.

  In addition, since the electrical resistance value of the MTJ element can be measured only by partially changing the on / off control of the transistors in the bit line driver BLDV and the digit line driver DLDV at the time of data writing, the control in the semiconductor device can be performed. Simplification can be achieved.

  FIG. 5 is a plan view showing a completed semiconductor package in the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a sectional view showing a completed semiconductor package in the semiconductor device according to the first embodiment of the present invention.

  5 and 6, semiconductor device 101 includes a semiconductor chip CP, an outer lead (external terminal) OR, an inner lead IR, and a die pad DP. The die pad DP also functions as an electrode for ground potential. The semiconductor chip CP is bonded (die bonding) on the die pad DP.

  A bonding wire WR is bonded to the bonding pad and the inner lead IR in the semiconductor chip CP, that is, wire bonding is performed. The inner lead IR and the outer lead OR may be bonded or integrated.

  The semiconductor chip CP is resin-sealed by, for example, a transfer molding method. The outer lead OR is plated by lead-free plating or the like mainly containing tin. The outer lead OR is bent.

  The bonding pad PD1 is connected to the external terminal EXT1. Bonding pads PD2 and PD3 are commonly connected to external terminal EXT2.

  Here, the MTJ element is evaluated in a state where the semiconductor chip is mounted on the silicon wafer, while the semiconductor chip on the silicon wafer is packaged by dicing or the like as shown in FIGS. 5 and 6. However, the MTJ element may not be evaluated.

  In this case, the pad PD3 needs to supply both the ground voltage and the measurement power supply voltage when the MTJ element is evaluated. However, after the MTJ element is evaluated, the pad PD3 is supplied with the same ground voltage as the pad PD2. That's fine. Therefore, when the semiconductor package is manufactured, the external terminals of the semiconductor device can be reduced by connecting the pads PD2 and PD3 to the common external terminal EXT2.

  Although the semiconductor device according to the first embodiment of the present invention is an MRAM in which data is written by a magnetic field generated by a current flowing through a digit line and a bit line, the present invention is not limited to this.

  For example, as described in the following embodiment, an STT (Spin Torque Transfer) -MRAM as described in Non-Patent Document 2 may be used. Further, not only the MRAM but also a memory using a resistor element as a memory element, such as a phase change memory, may be a memory that measures the resistance value of the memory element from the outside.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a semiconductor device that is an STT-MRAM. The contents other than those described below are the same as those of the semiconductor device according to the first embodiment.

  FIG. 7 is a schematic configuration diagram of the memory array 10 and its peripheral circuits according to the second embodiment of the present invention. In FIG. 7, the vertical direction on the paper corresponds to a memory cell row, and the horizontal direction on the paper corresponds to a memory cell column.

  Referring to FIG. 7, memory array 10 includes memory cells MC integrated and arranged in a matrix.

  In FIG. 7, representatively, memory cells MC0 to MC5, bit lines BL0 to BL2 provided corresponding to the memory cell columns, column select lines CSL0 and CSL1, source lines SL0 to SL2, and memory cell rows are provided. The word lines WL0 to WL3 provided are shown.

  The semiconductor device 102 according to the second embodiment of the present invention does not include the digit line driver DLDV and the digit line DL as compared with the semiconductor device 101.

  In bit line driver BLDV1, P channel MOS transistor TRB0 has a source connected to power supply node VDD, a drain connected to source line SL0, and a gate. N-channel MOS transistor TRB1 has a source connected to ground node VSS, a drain connected to source line SL0, and a gate. P-channel MOS transistor TRB4 has a source connected to power supply node VDD, a drain connected to source line SL1, and a gate. N-channel MOS transistor TRB5 has a source connected to ground node VSS, a drain connected to source line SL1, and a gate. P-channel MOS transistor TRB8 has a source connected to power supply node VDD, a drain connected to source line SL2, and a gate. N-channel MOS transistor TRB9 has a source connected to ground node VSS, a drain connected to source line SL2, and a gate.

  In memory cell MC0, MTJ element S0 has a first end connected to bit line BL0, and a second end. Cell transistor TRS0 has a gate connected to word line WL0, a drain connected to the second end of MTJ element S0, and a source connected to source line SL0. In memory cell MC1, MTJ element S1 has a first end connected to bit line BL0, and a second end. Cell transistor TRS1 has a gate connected to word line WL2, a drain connected to the second end of MTJ element S1, and a source connected to source line SL0. In memory cell MC2, MTJ element S2 has a first end connected to bit line BL1, and a second end. Cell transistor TRS2 has a gate connected to word line WL1, a drain connected to the second end of MTJ element S2, and a source connected to source line SL1. In memory cell MC3, MTJ element S3 has a first end connected to bit line BL1, and a second end. Cell transistor TRS3 has a gate connected to word line WL3, a drain connected to the second end of MTJ element S3, and a source connected to source line SL1. In memory cell MC4, MTJ element S4 has a first end connected to bit line BL2, and a second end. Cell transistor TRS4 has a gate connected to word line WL0, a drain connected to the second end of MTJ element S4, and a source connected to source line SL2. In memory cell MC5, MTJ element S5 has a first end connected to bit line BL2, and a second end. Cell transistor TRS5 has a gate connected to word line WL2, a drain connected to the second end of MTJ element S5, and a source connected to source line SL2.

  The bit line driver BLDV1 uses the ground voltage VSS supplied from the ground node VSS and the power supply voltage VDD supplied from the power supply node VDD based on the column selection result by the column decoder 25 at the time of data writing to the bit lines BL0 to BL2. The write current IWBL is supplied through the source lines SL0 to SL2. In addition, the bit line driver BLDV2 uses the ground voltage VSS supplied from the test node TN and the power supply voltage VDD supplied from the power supply node VDD based on the column selection result by the column decoder 25 at the time of data writing. A write current IWBL is caused to flow through -BL2 and source lines SL0-SL2. That is, the bit line drivers BLDV1 and BLDV2 pass the write current IWBL for writing data to the memory cells MC0 to MC5 to the bit lines BL0 to BL2 and the source lines SL0 to SL2, and write in the direction according to the logical value of the write data. A current IWBL is supplied.

  More specifically, for example, when the logical value of the write data is “0”, in bit line driver BLDV1, N channel MOS transistor TRB corresponding to the selected memory cell column receives a logic high level voltage at its gate. Turn on. P channel MOS transistor TRB corresponding to the selected memory cell column is turned off when the gate receives a logic high level voltage. In the bit line driver BLDV2, the P-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic low level voltage. In addition, N channel MOS transistor TRB corresponding to the selected memory cell column is turned off in response to a logic low level voltage at its gate. Then, the bit line driver through the bit line BL corresponding to the selected memory cell column, the MTJ element S corresponding to the selected memory cell row and the selected memory cell column, the on-state cell transistor TRS, and the source line SL corresponding to the selected memory cell column. A write current IWBL flows from BLDV2 to the bit line driver BLDV1.

  On the other hand, when the logical value of the write data is “1”, in the bit line driver BLDV1, the P-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic low level voltage. In addition, N channel MOS transistor TRB corresponding to the selected memory cell column is turned off in response to a logic low level voltage at its gate. In the bit line driver BLDV2, the N-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic high level voltage. P channel MOS transistor TRB corresponding to the selected memory cell column is turned off when the gate receives a logic high level voltage. Then, the bit line driver through the bit line BL corresponding to the selected memory cell column, the MTJ element S corresponding to the selected memory cell row and the selected memory cell column, the on-state cell transistor TRS, and the source line SL corresponding to the selected memory cell column. A write current IWBL flows from BLDV1 to the bit line driver BLDV2.

  The data read circuit RDC includes a bit line BL corresponding to the selected memory cell column, an MTJ element S corresponding to the selected memory cell row and the selected memory cell column, an on-state cell transistor TRS, and a source line SL corresponding to the selected memory cell column. The read current IR is supplied to the bit line driver BLDV1 via the. The data read circuit RDC reads data stored in the memory cells MC corresponding to the selected memory cell row and the selected memory cell column based on the amount of the read current IR.

  Next, a method for measuring the electrical resistance value of the MTJ element in the semiconductor device according to the second embodiment of the present invention will be described.

  When measuring the electrical resistance value of the MTJ element, the row selection circuits 20 and 21 and the column decoder 25 select a memory cell row and a memory cell column corresponding to the MTJ element S to be measured.

  In the bit line driver BLDV1, the P channel MOS transistor TRB corresponding to the selected memory cell column receives a logic high level voltage at the gate and is turned off. In addition, N channel MOS transistor TRB corresponding to the selected memory cell column is turned on upon receiving a logic high level voltage at its gate. In the bit line driver BLDV2, the N-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic high level voltage. P channel MOS transistor TRB corresponding to the selected memory cell column is turned off when the gate receives a logic high level voltage.

  In the bit line driver BLDV1, the N-channel MOS transistor TRB corresponding to the non-selected memory cell column is turned on when the gate receives a logic high level voltage. Further, the P channel MOS transistor TRB corresponding to the non-selected memory cell column is turned off when the gate receives a logic high level voltage. In the bit line driver BLDV2, the P channel MOS transistor TRB corresponding to the non-selected memory cell column receives a logic high level voltage at the gate and is turned off. Further, N channel MOS transistor TRB corresponding to the non-selected memory cell column is turned off in response to a logic low level voltage at its gate.

  Further, the word line WL corresponding to the selected memory cell row is driven to a logic high level by the row selection circuits 20 and 21. Then, the cell transistor TRS corresponding to the selected memory cell row is turned on when the gate receives a logic high level voltage.

  Then, the MTJ element S to be measured is electrically connected to the pad PD3 via the N channel MOS transistor TRB corresponding to the selected memory cell column in the bit line driver BLDV2.

  The column selection lines CSL0 and CSL1 are driven to a logic low level by the column decoder 25. N-channel MOS transistors TRC0 to TRC2 receive a logic low level voltage at their gates and are turned off.

  When a voltage is supplied from the test device 201 via the pad PD3, the N-channel MOS transistor TRB corresponding to the selected memory cell column in the bit line driver BLDV2, the MTJ element S to be measured, and the selected memory cell column in the bit line driver BLDV1 Current flows from test device 201 to ground node VSS via N channel MOS transistor TRB corresponding to. By measuring this current value, the electrical resistance value of the MTJ element S to be measured can be obtained.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here. Therefore, in the semiconductor device according to the second embodiment of the present invention, as in the semiconductor device according to the first embodiment, the electrical resistance value of the memory element is accurately measured and an increase in layout area is prevented. be able to.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic configuration diagram of a memory array 10 and its peripheral circuits according to a first embodiment of the present invention. In the semiconductor device concerning the 1st Embodiment of this invention, it is a figure which shows the connection of the pad for voltage supply and the external device at the time of the measurement of the electrical resistance value of an MTJ element. In the semiconductor device according to the first embodiment of the present invention, it is a diagram showing a connection between a voltage supply pad and an external device during normal operation. 1 is a plan view showing a completed semiconductor package in a semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view showing a completed semiconductor package in a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a schematic configuration diagram of a memory array 10 and its peripheral circuits according to a second embodiment of the present invention.

Explanation of symbols

  5 control circuit, 10 memory array, 20, 21 row selection circuit, 25 column decoder, 30, 35 read / write control circuit, 45, 50 row driver, 101, 102 semiconductor device, 201 test device, WL, WL0 to WL3 words Line, DL, DL0, DL1 digit line, BL, BL0-BL2 bit line, PS external power supply, SL source line, MC0-MC5, MC memory cell, S0-S5, SMTJ element (magnetic resistance element), TRS0-TRS5 , TRS cell transistor, DLDV digit line driver, TRD0, TRD1, TRD N-channel MOS transistor, BLDV1, BLDV2 bit line driver, RDC data read circuit, TRB0, TRB4, TRB8, TRB2, TRB6, TRB10, TRB P Yaneru MOS transistor, TRB1, TRB5, TRB9, TRB3, TRB7, TRB11, TRB N-channel MOS transistor, PD1～PD3 pad, CP semiconductor chip, OR outer lead (external terminal), IR inner lead, DP die pad.

Claims (5)

A storage element having a first terminal and a second terminal;
A current line coupled to the first terminal of the storage element;
A first driver coupled to the current line and configured to flow a bidirectional write current to the current line according to write data during a write operation to write data to the storage element;
A first pad for supplying a voltage;
A second pad for supplying a voltage;
A third pad for supplying a voltage,
The first pad and the third pad are coupled to the first driver;
The second pad is a semiconductor device coupled to the second terminal of the memory element. The semiconductor device further includes:
The current line, the first pad, and the second pad are coupled to each other, and the write current flows in both directions according to the write data through the current line together with the first driver during the write operation. The semiconductor device according to claim 1, further comprising a second driver. The first driver is:
A first transistor having a first conduction electrode coupled to the current line and a second conduction electrode coupled to the first pad;
A second transistor having a first conduction electrode coupled to the current line and a second conduction electrode coupled to the third pad;
The second driver is:
A third transistor having a first conduction electrode coupled to the current line and a second conduction electrode coupled to the first pad;
3. The semiconductor device according to claim 2 , comprising: a fourth transistor having a first conduction electrode coupled to the current line and a second conduction electrode coupled to the second pad. The semiconductor device further includes:
The memory device and the current coupled to the first pad, connected between the second pad and the second terminal of the memory element, and the write current together with the first driver during the write operation The semiconductor device according to claim 1, further comprising a second driver that flows in both directions according to the write data through a line. The semiconductor device further includes:
The first driver is:
A first transistor having a first conduction electrode coupled to the current line and a second conduction electrode coupled to the first pad;
A second transistor having a first conduction electrode coupled to the current line and a second conduction electrode coupled to the third pad;
The second driver is:
A third transistor having a first conduction electrode coupled to the second terminal of the memory element and a second conduction electrode coupled to the first pad;
5. The semiconductor device according to claim 4 , comprising: a fourth transistor having a first conduction electrode coupled to the second terminal of the memory element and a second conduction electrode coupled to the second pad.

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