JP5140859B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of magnetoresistive elements whose electric resistance values change according to the magnetization direction corresponding to the logical value of stored data.

  MRAM (Magnetic Random Access Memory) is a general term for a solid-state memory that stores data using the magnetization direction of a ferromagnetic material. In the MRAM, “1” and “0” correspond to whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or antiparallel to a certain reference direction. Further, a GMR element using a giant magnetoresistance effect (Giant Magneto Resistive effect: GMR (Giant Magneto Resistive) effect) and a magnetic tunnel effect (Tunneling Magneto Resistance effect: TMR (Tunneling Magneto) An MTJ (Magnetic Tunneling Junction) element or the like that utilizes the (resistive) effect) is used in the MRAM.

  The MTJ element is composed of a three-layer film of ferromagnetic layer / insulating layer / ferromagnetic layer, and a tunnel current flows through the insulating layer. The resistance value to the tunnel current changes according to the relationship between the magnetization directions of the two ferromagnetic layers.

  Here, as a method of reversing the magnetization direction of the ferromagnetic layer, there is known an external magnetization reversal method in which a current is passed in the vicinity of the memory cell to generate an external magnetic field and the magnetization direction of the ferromagnetic layer is reversed. (For example, refer nonpatent literature 1).

  As a method for reversing the magnetization direction of a ferromagnetic material, a spin injection magnetization reversal method is known (see, for example, Non-Patent Document 2). This is a method in which a current is directly applied to a memory cell to reverse the magnetization by the action of electrons' spin (direction). More specifically, this is a method of reversing the magnetization of the ferromagnetic layer by passing a current (hereinafter also referred to as a spin injection current) from one ferromagnetic layer of the TMR element to the other ferromagnetic layer. Since the spin injection current can have a smaller amount of current than the current for generating the external magnetic field, the spin injection magnetization reversal method can reduce the current consumption of the MRAM compared to the external magnetization reversal method.

  In the MRAM, for example, magnetoresistive elements are arranged in a matrix, and a plurality of word lines provided corresponding to the magnetoresistive element rows and a plurality of bit lines provided corresponding to the magnetoresistive element columns are provided. .

  In an MRAM employing the external magnetization reversal method, in order to write data to a certain magnetoresistive element, a write current is passed through the word line and bit line corresponding to the write target magnetoresistive element, thereby A data write magnetic field that affects the magnetization of the magnetoresistive element is generated.

  Here, there are variations in the data write characteristics of the magnetoresistive element, and in a magnetoresistive element in which data is easily written, that is, the magnetization direction is easily reversed, for example, it does not correspond to a bit line through which a write current flows, and the write current Even if the magnetoresistive element is compatible only with the word line through which the current flows, that is, the magnetoresistive element is arranged only in the vicinity of the word line through which the write current flows, the erroneous write is performed only by the data write magnetic field by the write current of the nearby word line There is.

In order to solve such a problem, for example, by dividing the word line and providing a word line driver for each divided word line, the divided word lines other than the divided word line corresponding to the magnetoresistive element to be written are provided. A configuration that prevents the write current from flowing is conceivable. With such a configuration, it is possible to prevent the magnetoresistive element from being erroneously written only by the data write magnetic field caused by the write current of the word line.
Takaharu Tsuji et al. "A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture", 2004 Symposium on VLSI Circuits Digest of Technical Papers pp.450-453 M. Hosomi et al. "A Novel Nonvolatile Memory with Spin torque Transfer Magnetization Switching: Spin-RAM", 2005 IEEE

  However, since the magnitude of the data write magnetic field is constant even if the number of magnetoresistive elements simultaneously writing data, that is, the number of magnetoresistive elements corresponding to the divided word lines is reduced, the magnitude of the write current flowing through the divided word lines is large. This is the same as when the word line is not divided. That is, the size of the transistors included in the word line driver is constant. For this reason, in the above configuration, there is a problem that the number of word line drivers increases and the layout area increases as the number of magnetoresistive elements simultaneously writing data, that is, as the number of divided word lines increases.

  Therefore, an object of the present invention is to provide a semiconductor device capable of preventing erroneous writing of data and preventing an increase in layout area.

  In summary, a semiconductor device according to an embodiment of the present invention is provided corresponding to a storage unit and connected between a first control line and a second control line corresponding to the corresponding storage unit. A plurality of third control lines and a diode provided corresponding to the storage unit and connected between the first control line and the third control line corresponding to the corresponding storage unit. The write circuit selects at least one of the plurality of third control lines at the time of data writing, and causes the write current to flow through the selected third control line, thereby selecting the selected third control. A data write magnetic field is generated that affects the magnetization of the magnetoresistive element corresponding to the line.

  According to the embodiment of the present invention, even if the number of third control lines increases in the storage unit column direction, the number of drivers connected to the second control lines is equal to the number of storage unit columns, It becomes constant. Even if the number of storage unit columns increases, the number of drivers connected to the first control line is equal to the number of storage unit rows and is constant. Therefore, erroneous writing of data can be prevented and an increase in layout area can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1 representatively shows a circuit corresponding to a 2 × 2 storage unit, and this circuit will be described below representatively.

  Referring to FIG. 1, a semiconductor device 101 includes a memory array 10 including storage units MU11, MU12, MU21, and MU22 arranged on a matrix, a write circuit 11, word line drivers WLD1 and WLD2, and divided word lines. Drivers WLED1, WLED2, bit line driver sections BLD1, BLD2, diodes D11, D12, D21, D22, word lines WLn, WLn + 1, word lines WWLn, WWLn + 1, write enable lines WWLEm, WWLEm + 1, and divided word lines DWWLnm, DWWL (n + 1) m, DWWLn (m + 1), DWWL (n + 1) (m + 1), and bit lines BL8m + 0 to BL8m + 7, BL8 (m + 1) +0 to BL8 (m + 1) +7.

  Each of word line drivers WLD1 and WLD2 may be referred to as word line driver WLD. Each of divided word line drivers WLED1 and WLED2 may be referred to as divided word line driver WLED. In addition, each of the diodes D11, D12, D21, and D22 may be referred to as a diode D. In addition, each of the word lines WLn and WLn + 1 may be referred to as a word line WL. In addition, each of word lines WWLn and WWLn + 1 may be referred to as word line WWL. Each of the write enable lines WWEn and WWEn + 1 may be referred to as a write enable line WWLE. Each of divided word lines DWWLnm, DWWL (n + 1) m, DWWLn (m + 1), and DWWL (n + 1) (m + 1) may be referred to as divided word line DWWL. Each of the bit lines BL8m + 0 to BL8m + 7 and BL8 (m + 1) +0 to BL8 (m + 1) +7 may be referred to as a bit line BL. In addition, each of the write data lines D0 to D7 may be referred to as a write data line D. In addition, each of the storage units MU11, MU12, MU21, and MU22 may be referred to as a storage unit MU.

  Hereinafter, the rows and columns of the plurality of storage units MU arranged in a matrix are also referred to as storage unit rows and storage unit columns, respectively.

  The storage unit MU includes a plurality of memory cells MC arranged in the storage unit column direction. Memory cell MC includes a magnetoresistive element M and a transistor TRC connected in series.

  The magnetoresistive element M changes its electrical resistance value according to the magnetization direction corresponding to the logical value of the stored data.

  The bit line BL is provided corresponding to the memory portion row. The word line WWLE is provided corresponding to the memory portion row. Word lines WL and WWL are provided corresponding to the storage unit columns. The divided word line DWWL is provided corresponding to the storage unit MU, and is connected between the write enable line WWLE and the word line WWL corresponding to the corresponding storage unit MU. The divided word line DWWL is disposed in the vicinity of each magnetoresistive element M in the corresponding storage unit MU.

  The diode D is provided corresponding to the storage unit MU, and is connected between the write enable line WWLE and the divided word line DWWL corresponding to the corresponding storage unit MU.

  The write circuit 11 selects the divided word line DWWL corresponding to the storage unit MU to be written at the time of data writing. That is, the write circuit 11 selects at least one of the plurality of divided word lines DWWL. The write circuit 11 generates a data write magnetic field that acts on the magnetization of the magnetoresistive element M corresponding to the selected divided word line DWWL by passing a write current through the selected divided word line DWWL. That is, the write circuit 11 applies the voltage level of the write enable line WWLE corresponding to the selected divided word line DWWL and the forward bias to the diode D connected to the selected divided word line DWWL. The voltage level of each word line WWL is controlled. As a result, a magnetic field is applied in the hard axis direction of the magnetoresistive element M.

  The write circuit 13 selects the bit line BL corresponding to the write target storage unit MU when writing data. That is, the write circuit 13 selects at least one of the plurality of bit lines BL. The write circuit 13 generates a data write magnetic field that acts on the magnetization of the magnetoresistive element M belonging to the storage unit row corresponding to the selected bit line BL by passing a write current through the selected bit line BL. Here, the write circuit 13 controls the bit line driver units BLD1 and BLD2 to cause a write current to flow in the direction according to the logical value of the write data through the selected bit line BL.

  Further, the write circuit 11 is configured so that the reverse bias is applied to the diode D connected to the unselected divided word line DWWL, and the voltage level of the write enable line WWLE corresponding to the unselected divided word line DWWL and The voltage level of each word line WWL is controlled.

  FIG. 2 is a diagram conceptually showing an operation at the time of data writing of the semiconductor device according to the embodiment of the present invention.

  Referring to FIG. 2, before performing a data write operation, write circuit 11 controls word line drivers WLD1, WLD2 and divided word line drivers WLED1, WLED2 to bring word lines WWLn, WWLn + 1 to a logic high level. And the write enable lines WWLEm and WWLEm + 1 are driven to a logic low level. As a result, a reverse bias is applied to the diodes D11, D12, D21, and D22, so that no write current flows through the divided word lines DWWLnm, DWWL (n + 1) m, DWWLn (m + 1), and DWWL (n + 1) (m + 1). .

  Next, the write circuit 11 controls the word line driver WLD1 and the divided word line driver WLED1 to drive the word line WWLn to the logic low level and drive the write enable line WWLEm to the logic high level. Thereby, since a forward bias is applied only to the diode D11, the write current WI flows only to the divided word line DWWLnm. Since reverse bias or zero bias is applied to the other diodes D12, D21, and D22, no current flows through the other divided word lines DWWL (n + 1) m, DWWLn (m + 1), and DWWL (n + 1) (m + 1). .

  In this way, by supplying a write current through the divided word line DWWLnm, data can be simultaneously written to the eight magnetoresistive elements M in the storage unit MU11 surrounded by a dotted line in FIG.

  By the way, in the configuration in which the word line is divided and a word line driver is provided for each divided word line, the write current does not flow to the divided word lines other than the divided word line corresponding to the magnetoresistive element to be written. As the number of magnetoresistive elements simultaneously writing data decreases, that is, as the number of divided word lines increases, the number of word line drivers increases and the layout area increases.

  However, in the semiconductor device according to the embodiment of the present invention, a plurality of divided words provided corresponding to the storage unit MU and connected between the write enable line WWLE and the word line WWL corresponding to the corresponding storage unit MU. A line DWWL and a diode D provided corresponding to the storage unit MU and connected between the write enable line WWLE and the divided word line DWWL corresponding to the corresponding storage unit MU. Then, the write circuit 11 selects at least one of the plurality of divided word lines DWWL and writes a write current through the selected divided word line DWWL to write the selected divided word line DWWL to the selected divided word line DWWL. A data write magnetic field acting on the magnetization of the corresponding magnetoresistive element M is generated.

  Thus, even if the number of word line divisions increases, the number of word line drivers WLD is equal to the number of storage unit columns and is constant. Even if the number of storage unit columns is increased, the number of divided word line drivers WLED is equal to the number of storage unit rows and is constant. Here, in the semiconductor device according to the embodiment of the present invention, a diode D is provided for each divided word line DWWL, but the diode occupies a smaller area than a MOS transistor. For this reason, it is possible to pass a large amount of current with a small layout area as compared with a configuration in which a word line driver is provided for each divided word line.

  In the semiconductor device according to the embodiment of the present invention, the write circuit 13 controls the bit line driver portions BLD1 and BLD2 to write current in the direction according to the logical value of the write data through the selected bit line BL. The data write magnetic field acting on the magnetization of the magnetoresistive element M belonging to the storage unit row corresponding to the selected bit line BL is generated. However, the present invention is not limited to this. As described in Non-Patent Document 2, a configuration in which a spin injection current is allowed to flow through a magnetoresistive element may be used.

  In the semiconductor device according to the embodiment of the present invention, the word line driver WLD and the divided word line driver WLED are provided on one side of the word line WWL and the write enable line WWLE, respectively. However, the present invention is not limited to this. Absent. By providing the word line driver WLD and the divided word line driver WLED on both sides of the word line WWL and the write enable line WWLE, respectively, the parasitic resistance of the wiring is prevented from changing due to the wiring resistance of the word line WWL and the write enable line WWLE. be able to.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows notionally the operation | movement at the time of the data writing of the semiconductor device which concerns on embodiment of this invention.

Explanation of symbols

  10 memory array, 11 write circuit, 101 semiconductor device, MU11, MU12, MU21, MU22 storage unit, WLD1, WLD2 word line driver, WLED1, WLED2 split word line driver, BLD1, BLD2 bit line driver unit, D11, D12, D21 , D22 Diode, WLn, WLn + 1, WWLn, WWLn + 1 Word line, WWLEm, WWLEm + 1 Write enable line, DWWLnm, DWWL (n + 1) m, DWWLn (m + 1), DWWL (n + 1) (m + 1) Split word line, BL8m + 0 to BL8m + 7, BL8 (M + 1) +0 to BL8 (m + 1) +7 Bit line, MC memory cell, M magnetoresistive element, TRC transistor.

Claims (1)

A plurality of storage units arranged on a matrix, each including a plurality of magnetoresistive elements whose electrical resistance values change according to the magnetization direction corresponding to the logical value of the stored data;
A plurality of first control lines provided corresponding to the storage unit rows;
A plurality of second control lines provided corresponding to the storage section row;
A plurality of third control lines provided corresponding to the storage unit and connected between the first control line and the second control line corresponding to the corresponding storage unit;
A diode provided corresponding to the storage unit and connected between the first control line and the third control line corresponding to the corresponding storage unit;
At the time of data writing, the selected third control line is selected by selecting at least one of the plurality of third control lines and passing a write current through the selected third control line. And a write circuit that generates a data write magnetic field that acts on the magnetization of the magnetoresistive element corresponding to.

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