JP4698712B2 - Thin film magnetic memory device - Google Patents

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a thin film magnetic memory device including a magnetic memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of MRAM devices will be dramatically improved by using a thin film magnetic body using a magnetic tunnel junction as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000., “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000., and “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7. 6, Feb. 2001. and the like.

  FIG. 34 is a schematic diagram showing the configuration of a memory cell having a magnetic tunnel junction (hereinafter simply referred to as “MTJ memory cell”).

  Referring to FIG. 34, the MTJ memory cell forms a tunnel magnetoresistive element TMR whose electric resistance changes according to the stored data level and a path of data read current Is passing through tunnel magnetoresistive element TMR during data reading. Access element ATR. Since access element ATR is typically formed of a field effect transistor, in the following, access element ATR is also referred to as access transistor ATR. Access transistor ATR is coupled between tunneling magneto-resistance element TMR and fixed voltage Vss (for example, ground voltage GND).

  Write word line WWL for instructing data write to MTJ memory cell, read word line RWL for executing data read, and data read and data write corresponding to the data level of stored data A bit line BL which is a data line for transmitting an electric signal is arranged.

  FIG. 35 is a conceptual diagram illustrating a data read operation from the MTJ memory cell. Referring to FIG. 35, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. A ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that is magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by the fixed magnetic layer FL, the tunnel barrier TB, and the free magnetic layer VL.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, data read current Is can be passed through the current path of bit line BL, tunneling magneto-resistance element TMR, access transistor ATR, and fixed voltage Vss (ground voltage GND).

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are the same (parallel), compared to the case where the magnetization directions of both are opposite (anti-parallel) directions. The tunnel magnetoresistive element TMR becomes small.

  Therefore, if the free magnetic layer VL is magnetized in the direction corresponding to the stored data, the voltage change caused in the tunnel magnetoresistive element TMR by the data read current Is differs depending on the stored data level. Therefore, for example, if data read current Is is passed through tunneling magneto-resistance element TMR after bit line BL is precharged to a constant voltage, the data stored in the MTJ memory cell is read by detecting the voltage of bit line BL. Can do.

FIG. 36 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 36, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL in the direction corresponding to the write data is supplied to write word line WWL and bit line BL. The magnetization direction of free magnetic layer VL is determined by data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 37 is a conceptual diagram for explaining the magnetization state of the tunnel magnetoresistive element at the time of data writing to the MTJ memory cell.

  Referring to FIG. 37, the horizontal axis H (EA) indicates a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and write word line WWL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy axis of magnetization, and the free magnetization layer VL is magnetized according to the level (“1” and “0”) of the stored data. Along the easy axis direction, it is magnetized in the parallel (identical) or antiparallel (opposite) direction to the fixed magnetization layer FL. Hereinafter, in this specification, the electric resistances of the tunnel magnetoresistive element TMR respectively corresponding to the two types of magnetization directions of the free magnetic layer VL are denoted by R1 and R0 (where R1> R0). The MTJ memory cell can store 1-bit data (“1” and “0”) corresponding to the two types of magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in the figure. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As shown by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold necessary to change the magnetization direction along the easy axis is lowered. be able to.

When the operating point at the time of data writing is designed as in the example of FIG. 37, the strength of the data writing magnetic field in the easy axis direction is H _WR in the MTJ memory cell that is the data writing target. Designed as such. That is, the value of the data write current flowing through the bit line BL or the write word line WWL is designed so that this data write magnetic field _HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  Further, in order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to pass a data write current of a predetermined level or more to both the write word line WWL and the bit line BL. . Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is parallel to fixed magnetic layer FL or in the opposite (anti-parallel) direction according to the direction of the data write magnetic field along the easy axis (EA). Magnetized. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

Thus, tunnel magnetoresistive element TMR changes its electric resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field, so that the two magnetizations of free magnetic layer VL in tunnel magnetoresistive element TMR By associating the direction with the level (“1” and “0”) of the stored data, nonvolatile data storage can be executed.
Roy Scheuerline and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Using FET Switches and Magnetic Tunnel Junctions in Each Cell Tunnel Junction and FET Switch in each Cell), (USA), 2000 Annual Meeting of the Institute of Electrical and Electronics Engineers International Solid State Circuits TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129 M. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 Electrotechnical Society of Japan Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131 Peter K. Naji et al., "256 kb, 3.0 volts and 1 transistor 1 magnetic tunnel junction type non-volatile magnetoresistive random access memory (A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM)" (USA), 2001 IEEE ISSCC Digest of Technical Papers (TA7.6), p. 122-123

  As described above, it is necessary to apply a magnetic field from both the corresponding write word line WWL and bit line BL to the MTJ memory cell (hereinafter also referred to as “selected memory cell”) as a data writing target. . However, the leakage magnetic field that acts on these MTJ memory cells other than the data write target (hereinafter also referred to as “non-selected memory cells”) from these write word lines W and bit lines is magnetic to the non-selected memory cells. It becomes noise. When such noise is large, there is a possibility that erroneous data writing is executed in the unselected memory cells.

  In particular, a non-selected memory cell belonging to the same row or the same column as the selected memory cell is applied with a magnetic field having a predetermined strength in either the easy magnetization axis direction or the hard magnetization axis direction. Therefore, the magnetic field acting on each non-selected memory cell corresponding to the adjacent row of the selected row or the adjacent column of the selected column is affected by the leakage magnetic field from the write word line of the selected row and the bit line of the selected column. Therefore, it is necessary to consider so as not to reach the outer region of the asteroid characteristic line shown in FIG.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a thin film with high operational reliability that prevents erroneous data writing in unselected memory cells due to magnetic noise. It is to provide a magnetic memory device.

  A thin film magnetic memory device according to the configuration of the present invention includes a memory array in which a plurality of magnetic memory cells each having a magnetic material magnetized in a direction according to stored data are arranged in a matrix, and a plurality of memory cells In order to selectively apply a data write magnetic field to a part, a plurality of write current lines that selectively receive supply of a data write current, and in the same direction as the plurality of write current lines outside the memory array Peripheral wiring arranged along the line. The current flowing through the peripheral wiring and the current flowing through the write current wiring closest to the peripheral wiring among the plurality of write current wirings are in opposite directions.

  Preferably, the thin film magnetic memory device further includes a plurality of write current driving circuits provided corresponding to the plurality of write current wirings, respectively, and the peripheral wiring is the closest of the plurality of write current driving circuits. Connected to the one corresponding to the write current wiring, the data write current is passed.

  A thin film magnetic memory device according to another configuration of the present invention includes a memory array in which a plurality of magnetic memory cells each having a magnetic material magnetized in a direction corresponding to stored data are arranged in a matrix, and a plurality of memories A plurality of write current wirings selectively receiving supply of a data write current to selectively apply a data write magnetic field to a part of the cell, and the same as the plurality of write current wirings outside the memory array And peripheral wiring arranged along the direction. The connection destination of the peripheral wiring is designed so that the period in which the data write current flows and the period in which the current flows in the peripheral wiring do not overlap each other.

  Preferably, the plurality of write current lines receive a data write current in a predetermined direction and apply a magnetic field along a hard axis to a part of the plurality of memory cells.

  Preferably, the plurality of write current lines receive a data write current in a direction corresponding to the write data, and cause a magnetic field along the easy magnetization axis to act on a part of the plurality of memory cells.

Alternatively, preferably, the peripheral wiring is arranged in a peripheral region of the memory array.
Preferably, the peripheral wiring is arranged in either the upper region or the lower region of the memory array.

  In the thin film magnetic memory device according to the present invention, the magnetic noise from the wiring arranged outside the memory array can be suppressed during data writing, so that the risk of erroneous data writing in the memory array can be suppressed. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of MRAM device 1 according to the embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 according to the embodiment of the present invention performs random access in response to external control signal CMD and address signal ADD, and inputs write data DIN and read data DOUT. Run the output. Data read and data write operations in the MRAM device 1 are executed, for example, at a timing synchronized with an external clock signal CLK. Alternatively, the operation timing may be determined internally without receiving the clock signal CLK from the outside.

  The MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 having a plurality of MTJ memory cells arranged in a matrix. A plurality of write word lines WWL and read word lines RWL are arranged corresponding to the respective MTJ memory cell rows (hereinafter also simply referred to as “memory cell rows”). Bit lines BL are arranged corresponding to the MTJ memory cell columns (hereinafter also simply referred to as “memory cell columns”).

  The MRAM device 1 further includes a row selection circuit 20, a column selection circuit 30, and read / write control circuits 50 and 60.

  The row selection circuit 20 performs row selection in the memory array 10 according to the row address RA indicated by the address signal ADD. Column selection circuit 30 performs column selection in memory array 10 in accordance with column address CA indicated by address signal ADD. A row address RA and a column address CA indicate a selected memory cell at the time of data writing and data reading.

  Read / write control circuits 50 and 60 write data to bit line BL of a memory cell column (hereinafter also referred to as “selected column”) corresponding to a selected memory cell at the time of data reading and data writing. A group of circuits arranged in a region adjacent to the memory array 10 in order to flow a current and a data read current.

FIG. 2 is a circuit diagram illustrating supply of a data write current according to the first embodiment.
FIG. 2 representatively shows a circuit configuration for executing a data write operation among peripheral circuit portions provided for memory array 10.

  Referring to FIG. 2, in memory array 10, MTJ memory cells MC are arranged in a matrix. Each MTJ memory cell MC has a configuration and data storage principle similar to those shown in FIGS. 34 to 37, and includes a tunnel magnetoresistive element TMR composed of a magnetic material magnetized in a direction corresponding to stored data. Access transistor ATR is included. Tunneling magneto-resistance element TMR and access transistor ATR are connected in series between corresponding bit line BL and fixed voltage Vss. As the access transistor ATR, a MOS transistor which is a field effect transistor formed on a semiconductor substrate is typically applied. Hereinafter, the fixed voltage Vss is also referred to as a ground voltage Vss.

  In particular, a configuration in which row selection is performed by hierarchical decoding will be described below. A plurality of MTJ memory cells MC arranged in the memory array 10 are divided into a plurality of memory blocks MB along the column direction. FIG. 2 representatively shows the first memory block MB1.

  In each memory block MB, a write word line WWL and a read word line RWL are provided corresponding to each memory cell row, and a bit line BL is arranged corresponding to each memory cell column.

  During data writing, a magnetic field in a direction along the hard axis of tunneling magneto-resistance element TMR is generated for write word line WWL of a selected memory cell row (hereinafter also referred to as “selected row”). A data write current is supplied, and a data write current for generating a magnetic field in the direction along the easy axis of tunneling magneto-resistance element TMR is supplied to bit line BL of the selected column. That is, it is necessary to control the direction of the data write current flowing through the bit line BL of the selected column according to the level of the write data DIN.

  Further, a main word line MWL provided in common to a plurality of memory blocks MB is arranged for every K (K: natural number) memory cell rows. FIG. 2 shows a case where K = 4. That is, in each memory block MB, four write word lines WWL are associated with one main word line MWL. FIG. 2 representatively shows a configuration corresponding to the j-th (j: natural number) main word line MWLj in the first memory block MB1. That is, in the memory block MB1, four write word lines WWL of the write word lines WWLj0, WWLj1, WWLj2, and WWLj3 are arranged corresponding to the main word line MWLj. The read word line RWL is also arranged in the same manner as the write word line WWL. That is, in the memory block MB1, four read word lines RWLj0 to RWLj3 are arranged corresponding to the main word line MWLj.

  Further, sub-decode signals SD0 to SD3 are transmitted at both ends of each memory block MB. Sub-decode signals SD0 to SD3 are set independently for each memory block MB and correspond to one main word line MWL in a memory block including a selected memory cell (hereinafter also referred to as “selected memory block”). It is selectively activated to select one of the four write word lines WWL and read word line RWL. For example, when write word line WWLj0 is selected, sub decode signal SD0 is activated to H level, and the remaining sub decode signals SD1 to SD3 are set to L level. On the other hand, in non-selected memory block MB, each of subdecode signals SD0 to SD3 is set to L level.

  In the following, signal line groups for transmitting subdecode signals SD0 to SD3 are also denoted as subdecode signal lines SD0 to SD3, respectively, using the same reference numerals.

  In the following, each of the write word line, the read word line, the bit line, and the main word line is collectively expressed. In the case, the symbols WWL, RWL, BL, and MWL are used respectively. When a specific write word line, read word line, bit line, and main write word line are indicated, these symbols are denoted by subscripts. The high voltage state (for example, power supply voltage Vcc) and low voltage state (for example, ground voltage Vss) of the signal and signal line are also referred to as “H level” and “L level”, respectively.

  In such a configuration, first, an operation of supplying a data write current to the bit line BL will be described.

  The read / write control circuit 50 has a bit line drive unit 51 composed of bit line drive circuits BDVa1 to BDVam provided corresponding to one ends of the bit lines BL1 to BLm, respectively. Similarly, the read / write control circuit 60 has a bit line drive unit 61 composed of bit line drive circuits BDVb1 to BDVbm provided corresponding to the other ends of the bit lines BL1 to BLm, respectively. In the following, the bit line drive circuits BDVa1 to BDVam are collectively referred to as bit line drive circuit BDVa, and the bit line drive circuits BDVb1 to BDVbm are also collectively referred to as bit line drive circuit BDVb.

  Further, column selection lines CSL1 to CSLm are provided corresponding to the memory cell columns, respectively. Hereinafter, the column selection lines CSL1 to CSLm are also collectively referred to as a column selection line CSL. Column select line CSL is activated to H level in a selected column and deactivated to L level in a non-selected column.

  Each bit line drive circuit BDVa controls the voltage on one end side of the corresponding bit line BL in accordance with the corresponding column selection line CSL and write data DIN. In contrast, each bit line drive circuit BDVb controls the voltage on the other end side of the corresponding bit line BL according to the corresponding column selection line CSL and the inverted data / DIN of the write data. In the selected column, bit line drive circuits BDVa and BDVb set one end side and the other end side of corresponding bit line BL to one of H level and L level according to the level of write data DIN. For example, when write data DIN is at the H level (“1”), bit line drive circuit BDVa couples one end of the bit line of the selected column to power supply voltage Vcc, and bit line drive circuit BDVb is a bit of the selected column. The other end of the line is connected to the ground voltage Vss. As a result, a data write current flows in the direction from bit line drive unit 51 to 61 on the bit line of the selected column.

  In contrast, when write data DIN is at L level (“0”), bit line drive circuits BDVa and BDVb connect one end side and the other end side of the bit line of the selected column to ground voltage Vss and power supply voltage Vcc. And combine with each. As a result, a data write current in the direction opposite to that when write data DIN is at the H level (“1”) flows on the bit line of the selected column. On the other hand, in the non-selected column, bit line drive circuits BDVa and BDVb connect one end side and the other end side of corresponding bit line BL to ground voltage Vss. As a result, no data write current flows on the bit line of the non-selected column.

  Next, current supply to the write word line WWL at the time of data writing will be described. In the following, it is assumed that the write word lines WWLj0 and WWLj1 correspond to even rows, and the write word lines WWLj2 and WWLj3 correspond to odd rows.

  For each write word line WWL, a write drive circuit WWD is provided for controlling the current supply to the write word line according to the row selection result. In each memory block MB, the write drive circuits WWD are alternately arranged every other row corresponding to one of both ends of the write word line WWL. For example, as shown in FIG. 2, write drive circuits WWDj0 and WWDj1 corresponding to even rows and write drive circuits WWDj2 and WWDj3 corresponding to odd rows are arranged in opposite directions.

  The other end of each write word line WWL where the write drive circuit WWD is not arranged is connected to the ground voltage Vss regardless of the row selection result. Write word lines corresponding to even-numbered rows including write word lines WWLj0 and WWLj1 are directly connected to ground voltage Vss in a region opposite to row selection circuit 20. The write word line group corresponding to the odd-numbered rows including the write word lines WWLj2 and WWLj3 is directly connected to the ground voltage Vss in the region on the row selection circuit 20 side.

  Each write drive circuit WWD supplies the data write current Iww to the write word line when the corresponding write word line is selected, and the current ΔIww when the adjacent row is selected. Supply to word line. FIG. 2 shows a configuration of write drive circuits WWDj0 and WWDj1 provided corresponding to write word lines WWLj0 and WWLj1 as an example.

  Write drive circuit WWDj0 includes a driver transistor 101 connected between sub decode signal line SD0 and one end of write word line WWLj0, and a driver transistor connected between power supply voltage Vcc and one end of write word line WWLj0. 102 and driver transistors 101 # and 102 # connected in series between one end of write word line WWLj0 and ground voltage Vss. Driver transistors 101 and 102 are P channel MOS transistors, and driver transistors 101 # and 102 # are N channel MOS transistors.

  Driver transistors 101 and 101 # have their gates connected to node N1, and driver transistors 102 and 102 # have their gates connected to node N2. That is, driver transistors 101 and 101 # are complementarily turned on / off, and driver transistors 102 and 102 # are complementarily turned on / off.

  / MWLj indicating the inversion level of the corresponding main word line MWLj is input to node N1. For example, such a configuration is realized by providing an inverter (not shown) between the main word line MWLj and the node N1.

  Logic circuit 107 includes a first OR gate that outputs an OR operation result of sub-decode signals SD2 and SD3, and a second OR gate that outputs an output of the first OR gate and an OR operation result of sub-decode signal SD0. The output of the second OR gate and the NAND gate for outputting the NAND logic operation result of the voltage level of the main word line MWL to the node N1. As a result, the voltage level of node N2 is set to L level when the row (write word line WWLj0) or the adjacent row (write word line WWLj2 or WWLj3) is selected as the data write target, and the row and adjacent row If none of the rows is subject to data writing, it is set to H level.

  As a result, when corresponding main word line MWLj is activated to H level, driver transistor 101 is turned on and driver transistor 101 # is turned off. Therefore, driver transistor 101 supplies current to write word line WWLj0 when main word line MWLj is activated to H level and subdecode signal line SD0 is driven to H level.

  When the node N2 is set to the L level, that is, the driver transistor 102, when either the row corresponding to the write word line WWLj0 or the adjacent row (write word lines WWLj2, WWLj3) is selected as the data write target. A current is supplied to the write word line WWLj0.

  As a result, in write word line WWLj0, when the row is selected, a current corresponding to the sum of the current driving capabilities of driver transistors 101 and 102 is supplied as data write current Iww. Further, when an adjacent row is selected, a current ΔIww corresponding to the current driving capability of the driver transistor 102 is supplied. The current drive capability of driver transistors 101 and 102 for driving the current supplied to write word line WWL can be adjusted by designing the transistor size (ratio of gate width / gate length), for example.

  On the other hand, when neither the row nor the adjacent row is selected, current supply from write drive circuit WWDj0 is not executed for the corresponding write word line WWLj0.

  The write drive circuit WWDj1 provided corresponding to the write word line WWLj1 has a slightly different decoding configuration because one of the adjacent rows is associated with the next main word line MWLj + 1 (not shown).

  In write drive circuit WWDj1, driver transistor 101 is provided between sub-decode signal line SD1 and write word line WWLj1. Since the arrangement of driver transistors 102 and 101 #, 102 # is similar to that of write drive circuit WWDj0, detailed description will not be repeated.

  In write drive circuit WWDj1, the gate voltages of driver transistors 102 and 102 #, that is, the level of node N2, is set by logic circuit 108.

  The logic circuit 108 outputs an OR gate that outputs an OR operation result of the subdecode signals SD1 and SD3, an AND gate that outputs an AND logic operation result of the output of the OR gate and the voltage level of the main word line MWL, and a subdecode signal. An AND gate that outputs an AND logic operation result of SD2 and the voltage level of the next main word line MWLj + 1, and a NOR gate that outputs a NOR operation result of each output of the two AND gates to the node N2 .

  As a result, the voltage level of the node N2 is set to the L level when either the relevant row (write word line WWLj1) or the adjacent row (write word line WWLj3 or write word line WWL (j + 1) 2 not shown) is selected. When it is set and neither of the row and the adjacent row is selected, the node N2 is set to the H level. That is, the logic circuit 107 and the logic circuit 108 have the same function, and in each write drive circuit WWD, the node N2 is set to the L level when either the row or the adjacent row is selected. Otherwise, it is set to H level.

  Similarly to write drive circuits WWDj1 and WWDj0, subdecode signals SD2 and SD3 are transmitted to write drive circuits WWDj2 and WWDj3, and other subdecodes necessary for determining the selection of the row and adjacent rows. It is assumed that signals SD0 and SD1 are also transmitted. Write drive circuit WWDj3 has the same configuration as write drive circuit WWDj0, since sub-decode is performed because corresponding write word line WWLj3 and write word lines WWLj0 and WWLj1 in adjacent rows all correspond to the same main word line MWLj. A configuration in which signals are appropriately replaced is applied. On the other hand, write drive circuit WWDj2 corresponds to main word line MWLj-1 in which one of adjacent write word lines is different, so that the same configuration as write drive circuit WWDj1 is applied, so that the subdecode signal and the main word It is necessary to replace the lines appropriately.

  As described above, each write drive circuit WWD supplies the data write current Iww to the corresponding write word line WWL using the driver transistors 101 and 102 when the row is selected. Each write drive circuit WWD supplies a current ΔIww smaller than the data write current Iww using only the driver transistor 102 when an adjacent row is selected.

  Since the write drive circuit WWD configured in this way is alternately arranged for each row corresponding to the write word line WWL, the data write flowing in the write word line of the selected row is written to the write word line of the adjacent row. A current ΔIww (hereinafter also referred to as “−ΔIww” in consideration of the current direction) is passed in the direction opposite to the current Iww. For example, when the memory cell corresponding to write word line WWLj0 is selected, the data write current in the direction away from row selection circuit 20 to write word line WWLj0 of the selected row (the direction from left to right in FIG. 2). While Iww is supplied, the write word lines WWLj2 and WWLj3 in the adjacent rows are approached to the row selection circuit 20 (in the direction from right to left in FIG. 2), that is, the write word lines WWLj in the selected row. A current −ΔIww is caused to flow in a direction opposite to the upper data write current Iww.

  Therefore, the leakage magnetic field acting on the non-selected memory cell by the data write current Iww of the selected row can be canceled by the magnetic field generated by the current −ΔIww of the adjacent row. As a result, it is possible to prevent the erroneous writing of data to unselected memory cells including the adjacent row, and to improve the operation reliability of the MRAM device. In the following, the current ΔIww flowing in the adjacent row is also referred to as “magnetic field cancellation current”, and the magnetic field generated by the magnetic field cancellation current is also referred to as “cancellation magnetic field”.

  In each write word line WWL, the data write current Iww that flows when the corresponding memory cell row is selected and the current ΔIww that flows when the adjacent row is selected are in the same direction. That is, since the current supply by each write drive circuit WWD is limited to a certain direction, the circuit configuration is not complicated.

  By alternately arranging the write drive circuits WWD for each row, the supply of such a magnetic field canceling current ΔIww is realized by two kinds of voltages, the power supply voltage Vcc and the ground voltage Vss. In other words, if the write drive circuit WWD having the configuration shown in FIG. 2 is concentrated on one side of the write word line WWL, it is necessary to further supply a negative voltage to each write drive circuit WWD. Further, the alternate arrangement can contribute to miniaturization of the MRAM device by relaxing the arrangement layout of the write drive circuit WWD.

  As described with reference to FIG. 37, the magnetization direction of tunneling magneto-resistance element TMR of the selected memory cell is set by the magnetic field along the easy axis, that is, the direction of the data write current flowing through bit line BL. That is, the direction of the data write current flowing through the write word line WWL does not directly affect the magnetization direction of the tunnel magnetoresistive element TMR. Therefore, even if the direction of the data write current flowing through the write word line WWL is set to the opposite direction in the odd and even rows, the data write operation is not hindered.

  Although detailed illustration is omitted in FIG. 2, the data read operation for the memory array 10 will be briefly described. At the time of data reading, a read word line driver (not shown) activates the read word line RWL of the selected row to H level based on the main word line MWL and the subdecode signals SD0 to SD3. In response, access transistor ATR is turned on in each MTJ memory cell MC of the selected row. Thereby, each of bit lines BL1-BLm is coupled to ground voltage Vss through tunneling magneto-resistance element TMR. Further, by coupling the bit line of the selected column with a predetermined voltage different from the ground voltage Vss, if a voltage difference is generated at both ends of the tunnel magnetoresistive element TMR, a current corresponding to the storage data of the selected memory cell is It can be generated in the bit line of the selected column. As a result, data reading from the selected memory cell can be executed by detecting the passing current of the bit line of the selected column.

  As described above, according to the configuration according to the first embodiment, a magnetic field canceling current for canceling a leakage magnetic field generated by a predetermined data write current can be supplied to each write word line in an adjacent row. . Further, in each of the write drive circuits that control the two types of current supply, the magnetic field canceling current is supplied using a part of the driver transistor that is turned on when the data writing current is supplied. The arrangement area of the driver transistor group used for supplying the write current and the magnetic field canceling current can be reduced. As described above, since the write drive circuit WWD is arranged for each write word line WWL, the reduction of the circuit area has a great effect on the area reduction of the entire MRAM device.

[Modification of Embodiment 1]
In the first embodiment, the configuration in which the magnetic field cancellation current in the direction opposite to the data write current is supplied in the row adjacent to the selected row has been described. However, in such a configuration, the outermost memory cell row of the memory array has only one adjacent row, so that the magnetic field applied during data writing is different compared to other memory cell rows. Come. As a result, non-uniformity of the data writing operation occurs in the memory array 10 and the operation margin may be impaired.

  In the modification of the first embodiment, a configuration in which a canceling magnetic field can be applied to the memory cell row at the end of the memory array as in the case of other memory cell rows will be described.

FIG. 3 is a circuit diagram illustrating the supply of the data write current according to the modification of the first embodiment.
FIG. 3 illustrates the configuration of the portion corresponding to the leading main word line MWL1 in the memory block MB1 in order to illustrate the configuration of the end portion of the memory array 10.

  In this region, read word lines RWL10-13 and write word lines WWL10-13 are arranged corresponding to the memory cell rows, respectively, and write drive circuits WWD10-WWD13 are arranged corresponding to the write word lines WWL10-WWL13, respectively. Has been placed.

  Since the configuration and operation of write drive circuits WWD10 to WWD13 are similar to those of write drive circuits WWDj0 to WWDj3 shown in FIG. 2, detailed description will not be repeated.

  In the configuration according to the modification of the first embodiment, a dummy memory cell row is arranged further outside the outermost memory cell row corresponding to write word line WWL12.

  Corresponding to the dummy memory cell row, a dummy write word line DWWL and a dummy read word line DRWL are arranged. Further, a dummy write drive circuit WWDd is provided corresponding to the dummy write word line DWWL.

  The dummy write drive circuit WWDd includes a driver transistor 102d connected between the power supply voltage Vcc and one end of the dummy write word line DWWL, and a driver connected between one end of the dummy write word line DWWL and the ground voltage Vss. A transistor 103d. The current driving capability of the driver transistor 102d is designed in the same manner as the driver transistor 102 in each write drive circuit WWD.

  Driver transistors 102d and 103d are complementarily turned on or off in accordance with the output of logic gate 109. Logic gate 109 outputs a NAND logic operation result between the voltage level of main word line MWL1 and subdecode signal SD2. Therefore, the driver transistor 102d is turned on when the main word line MWL1 is activated and the outermost memory cell row (corresponding to the write word line WWL12) is selected, and turned off otherwise.

  As a result, for dummy write word line DWWL, when the endmost memory cell row is selected and data write current Iww is supplied to write word line WWL12, magnetic field cancellation current −ΔIww is applied. Become. Therefore, the canceling magnetic field can be applied to the outermost memory cell row as well as the other memory cell rows.

  That is, since the data write characteristics and the erroneous data write resistance can be made to be the same as those of other memory cell rows even in the outermost memory cell row of the memory array 10, the data write characteristics in the memory array 10 can be improved. Uniformity can be achieved.

  For the purpose of supplying only the magnetic field canceling current ΔIww, only the dummy write word line DWWL needs to be disposed, and the dummy memory cell and the dummy read word line DRWL are not necessarily disposed. However, if the design pattern suddenly changes at the end of the memory array, an error is likely to occur in the finish of the shape / dimension at the boundary, so the dummy memory cell and the dummy read word line DRWL are arranged, It is desirable to design in the same manner as the memory cell rows in the memory array 10.

[Embodiment 2]
In the configuration according to the first embodiment, data write current Iww is supplied by driving sub decode signal lines SD0 to SD3 to H level. The magnetic field canceling current ΔIww is driven by the power supply voltage Vcc.

  In the second embodiment, a desirable arrangement of a voltage source and a current source for supplying these data write current and magnetic field cancellation current will be described.

  FIG. 4 is a block diagram illustrating a first configuration example of a data write current and magnetic field cancel current supply system according to the second embodiment.

  Referring to FIG. 4, in the first configuration example according to the second embodiment, the configuration of memory array 10 and the configuration and operation of each write drive circuit WWD are the same as those described in the first embodiment. Detailed description will not be repeated.

  In FIG. 4, SD drive circuits 140 and 140 # for driving sub-decode signal lines SD0 to SD3, current source circuits 111 and 111 # for generating magnetic field cancellation current ΔIww, and current lines 113 and 113 are further provided. # Shows ground lines GL and GL # and ground nodes 114 and 114 # for connecting one end side or the other end side of each write word line WWL to ground voltage Vss, respectively. Current lines 113 and 113 # and ground lines GL and GL # are arranged along the column direction, similarly to sub-decode signal lines SD0 to SD3.

  SD drive circuit 140, current source circuit 111, current wiring 113 and ground node 114 are provided corresponding to even-numbered write word lines (for example, WWLj0, WWLj1) and write drive circuits (for example, WWDj0, WWDj1), and are driven by SD. Circuit 140 #, current source circuit 111 #, current line 113 #, and ground node 114 # are provided corresponding to odd-numbered write word lines (for example, WWLj2, WWLj3) and write drive circuits (for example, WWDj2, WWDj3).

  Subdecode signal lines SD0 and SD1 transmit the data write current driven by SD drive circuit 140 to the write drive circuits in even rows, and subdecode signal lines SD2 and SD3 are driven by SD drive circuit 140 #. The data write current is transmitted to the odd-numbered write drive circuits. Similarly, current line 113 transmits the data write current supplied from current source circuit 111 to the even-numbered write drive circuit, and current line 113 # receives the data write current supplied from current source circuit 111 #. Is transmitted to the odd-numbered write drive circuit.

  On the other hand, ground line GL is provided to guide the data write current and cancel current that have passed through even-numbered write word lines to ground node 114, and ground line GL # has passed through odd-numbered write word lines. , Provided to guide data write current and cancel current to ground node 114 #.

  In the first configuration example shown in FIG. 4, SD drive circuits 140 and 140 #, current source circuits 111 and 111 #, current lines 113 and 113 #, and ground nodes 114 and 114 # are connected to memory array 10. Are concentrated on one side of the adjacent region in the column direction.

  Thus, for example, when an even-numbered row (write word lines WWLj0, WWLj1) is selected, data write current is applied to SD drive circuit 140 and current source circuit 111-subdecode signal lines SD0, SD1 and current wiring 113-selected row. The write drive circuit-the write word line of the selected row-the ground wiring GL-the path of the ground node 114 flows, and the magnetic field canceling current is the current source circuit 111 # -current wiring 113 # -the adjacent row write drive circuit-the adjacent row write It flows through the path of word line-ground wiring GL # -ground node 114 #. At this time, the direction of the data write current flowing through sub-decode signal lines SD0 and SD1 and current line 113 is opposite to the direction of the magnetic field cancel current flowing through ground line GL #, and the data write current flowing through ground line GL And the magnetic field cancellation current flowing through the current wiring 113 # is also in the opposite direction.

  Therefore, with respect to data write current Iww and magnetic field canceling current ΔIww, magnetic fields from current paths other than the write word line in the selected row and adjacent rows act in directions that cancel each other in memory array 10.

  When an odd row is selected, a data write current flows through sub-decode signal lines SD2 and SD3, current line 113 # and ground line GL #, and a magnetic field canceling current flows through current line 113 and ground line GL. On the wiring, the data write current Iww and the magnetic field cancellation current ΔIww flow in opposite directions. Therefore, as in the case of selecting even-numbered rows, the magnetic fields from the current paths other than the write word line due to the data write current Iww and the magnetic field cancel current ΔIww act in the direction of canceling each other in the memory array 10.

  As a result, in addition to the effect of the configuration according to the first embodiment, it is possible to further reduce the magnetic disturbance to the memory array 10 and to stabilize the data writing.

  FIG. 5 is a block diagram illustrating a second configuration example of the data write current and magnetic field cancel current supply system according to the second embodiment.

  Referring to FIG. 5, in the second configuration example according to the second embodiment, SD drive circuit 140, current source circuit 111 and ground node 114 # are compared with the first configuration example shown in FIG. SD drive circuit 140 #, current source circuit 111 #, and ground node 114 are different from each other in that they are arranged in regions opposite to each other across memory array 10. Since the configuration of the other parts is the same as that of FIG. 4, detailed description will not be repeated.

  In the configuration shown in FIG. 5, the data write current on sub decode signal lines SD0 to SD3, current lines 113 and 113 #, and ground lines GL and GL # is selected regardless of whether odd or even lines are selected. In addition, the directions of the magnetic field cancellation current can be opposite to each other. Therefore, it is possible to reduce the magnetic disturbance to the memory array 10 due to the magnetic field from the current path other than the write word line due to the data write current Iww and the magnetic field cancellation current ΔIww, and to stabilize the data writing. .

  Further, according to the second configuration example shown in FIG. 5, the SD drive circuit 140, the current source circuit 111, and the ground node 114 are arranged in regions opposite to each other across the memory array 10, and SD drive circuit 140 #, current source circuit 111 #, and ground node 114 # are grounded in regions opposite to each other across memory array 10. Thereby, the current path length can be made constant for each of the data write current Iww and the magnetic field cancellation current ΔIww regardless of the position of the selected memory cell row.

  Furthermore, the electrical resistance value per unit length is similarly designed for each of sub-decode signal lines SD0 to SD3, current lines 113 and 113 #, and ground lines GL and GL #. Thereby, the data write current Iww and the magnetic field cancellation current ΔIww are made uniform regardless of the memory cell row selection result. As a result, magnetic noise caused by the data write current Iww and magnetic field cancellation current ΔIww from the current path other than the write word line WWL is suppressed, and the uniformity of the data write characteristics in the memory array 10 can be further improved. It becomes possible. Therefore, a more stable data writing operation can be executed.

  FIG. 6 is a block diagram illustrating a third configuration example of the data write current and magnetic field cancel current supply system according to the second embodiment.

  Referring to FIG. 6, according to the third configuration example according to the second embodiment, in addition to the second configuration example shown in FIG. 5, SD drive circuit 140 corresponding to an even-numbered row includes subdecode signal lines. They are arranged corresponding to both ends of SD0 and SD1, respectively. Similarly, the current source circuits 111 are also provided corresponding to both ends of the current wiring 113, that is, corresponding to regions adjacent to each other in the column direction of the memory array 10. The ground node 114 is also provided corresponding to both ends of the ground wiring GL.

  Similarly, SD drive circuit 140 # and current source circuit 111 # corresponding to the odd-numbered rows are also arranged corresponding to both ends of sub-decode signal lines SD2 and SD3 and current line 113 #, respectively. Similarly, ground node 114 # is also arranged corresponding to both ends of ground line GL #. Since the configuration of other parts is the same as that of FIG. 5, detailed description will not be repeated.

  By adopting such a configuration, in the third configuration example shown in FIG. 6, as in the second configuration shown in FIG. 5, subdecode signal lines SD0 to SD3, current lines 113, 113 # and Magnetic noise to the memory array 10 from the ground lines GL and GL # can be suppressed, and the data write current Iww and the magnetic field cancel current ΔIww can be made uniform regardless of the selection of the memory cell row.

  Furthermore, the current path lengths of the data write current Iww and the magnetic field cancellation current ΔIww are made to be larger than that of the second configuration example shown in FIG. 5 by supplying current from both sides of each signal line or current wiring. It can be shortened effectively. As a result, it is possible to further reduce the current consumption by reducing the electrical resistance of these current paths.

[Modification of Embodiment 2]
In the first and second embodiments, the configuration in which data write current Iww is driven by SD drive circuits 140 and 140 # that drive sub-decode signal lines SD0 to SD3 has been described. In contrast, a dedicated current source circuit may be provided, and each write drive circuit may have a decoding function only.

  FIG. 7 is a block diagram illustrating a first configuration example of a data write current and magnetic field cancellation current supply system according to a modification of the second embodiment.

  Referring to FIG. 7, in the first configuration example according to the modification of the second embodiment, write drive circuits 131 and 132 are substituted for each of write drive circuits WWD as compared to the configuration shown in FIG. Is different from SD drive circuits 140 and 140 # in that current source circuits 110 and 110 # for generating data write current Iww are arranged, respectively. In other words, in the configuration shown in FIG. 7, data write current Iww is supplied by current wirings 112 and 112 # newly provided along the column direction. Although the subdecode signal lines SD0 to SD3 are not shown, these signal lines are simply arranged as voltage wirings for transmitting the subdecode signals SD0 to SD3 to the write drive circuits 131 and 132. And

  FIG. 8 is a circuit diagram showing a configuration of write drive circuits 131 and 132 shown in FIG.

  Referring to FIG. 8, write drive circuit 131 includes driver transistor PT1 connected between current line 112 (or 112 #) and corresponding write word line WWL, corresponding write word line WWL and ground voltage Vss. Driver transistor NT1 connected between the two transistors. Write drive circuit 132 includes driver transistor PT2 connected between current line 113 (or 113 #) and corresponding write word line WWL. Driver transistors PT1 and PT2 are formed of P channel MOS transistors, and driver transistor NT1 is formed of an N channel MOS transistor.

  Driver transistor PT1 has its gate connected to node N1, and driver transistor PT2 has its gate connected to node N2. The output of logic gate 134 that outputs the AND logic operation result of nodes N1 and N2 is input to the gate of driver transistor NT1.

  The selection circuit 26 sets the node N1 to L level when the row is selected, and to H level otherwise. Further, the selection circuit 26 sets the node N2 to the L level when any one of the row or the adjacent row is selected, and sets the node N2 to the H level in other cases. The selection circuit 26 corresponds to a part of the function of the row selection circuit 20.

  With such a configuration, when the row is selected, data write current Iww is supplied to write word line WWL by driver transistors PT1 and PT2. When an adjacent row is selected, the magnetic field cancellation current ΔIww is supplied only by the driver transistor PT2. When both of the driver transistors PT1 and PT2 are turned off, the driver transistor NT1 is turned on to fix the corresponding write word line WWL to the ground voltage Vss.

  Referring again to FIG. 7, the amount of current generated by current source circuits 110 and 111 is designed in the same manner as driver transistors 101 (101 #) and 102 (102 #) shown in FIG.

  Alternatively, as a configuration in which node N2 is set to L level only when an adjacent row is selected, a data write current can be supplied by driver transistor PT1, and a magnetic field canceling current can be supplied by driver transistor PT2. In this case, the current supply amounts of the current source circuits 110 and 111 shown in FIG. 7 may be designed in accordance with the data write current Iww and the magnetic field cancellation current ΔIww, respectively.

  As described above with reference to FIG. 5, the data write current Iww may be changed to the general configuration in which the write drive circuit is changed to supply the data write current Iww by the current source circuits 110 and 110 #. It is possible to further reduce magnetic disturbance from the current path other than the write word line to the memory array 10 due to Iww and the magnetic field cancellation current ΔIww, thereby stabilizing data writing.

  FIG. 9 is a block diagram illustrating a second configuration example of the data write current and magnetic field cancel current supply system according to the modification of the second embodiment.

  Referring to FIG. 9, in the second configuration example according to the modification of the second embodiment, write drive circuit 131 is substituted for each of write drive circuits WWDj0 to WWDj3 as compared to the configuration shown in FIG. And 132, the current source circuits 110 and 110 # instead of the SD drive circuits 140 and 140 #, and the current wirings 112 and 112 # newly provided, the data write current Is different from that supplied. Since these differences are similar to the differences between FIG. 4 and FIG. 7 already described, detailed description will not be repeated. 9 is the same as that of FIG. 5, and therefore detailed description will not be repeated.

  Therefore, even when the configuration of the write drive circuit is changed and the data write current Iww is supplied by the current source circuits 110 and 110 #, the data write current Iww is similar to the configuration shown in FIG. In addition, for each of the magnetic field cancellation current ΔIww, the current path length can be made constant regardless of the position of the selected memory cell row.

  Furthermore, each of current lines 112 and 112 #, current lines 113 and 113 #, and ground lines GL and GL # are designed to have the same electrical resistance value per unit length. As a result, the current amounts of the data write current Iww and the magnetic field cancellation current ΔIww are made uniform regardless of the selection result of the memory cell row.

  As a result, magnetic noise caused by the data write current Iww and the magnetic field cancellation current ΔIww from the current path other than the write word line can be suppressed, and the uniformity of the data write characteristics in the memory array 10 can be further improved. It becomes.

  FIG. 10 is a block diagram illustrating a third configuration example of the data write current and magnetic field cancellation current supply system according to the modification of the second embodiment.

  Referring to FIG. 10, in the third configuration example according to the modification of the second embodiment, write drive circuit 131 is substituted for each of write drive circuits WWDj0 to WWDj3 as compared to the configuration shown in FIG. 6. And 132, the current source circuits 110 and 110 # instead of the SD drive circuits 140 and 140 #, and the current wirings 112 and 112 # newly provided with the data write current. Different points are supplied. Since these differences are similar to the differences between FIG. 4 and FIG. 7 already described, detailed description will not be repeated. 10 is the same as that of FIG. 6, and detailed description thereof will not be repeated.

  Therefore, even if the configuration of the write drive circuit is changed so that the data write current Iww is supplied by the current source circuits 110 and 110 #, the same effect as the configuration shown in FIG. 6 can be obtained. it can. In other words, in addition to the effect of the configuration shown in FIG. 9, the current path lengths of the data write current Iww and the magnetic field cancellation current ΔIww can be effectively shortened, so that the current consumption can be further reduced. Become.

[Embodiment 3]
In the third embodiment, a configuration in the case where each memory block MB is divided into a plurality of banks in the second embodiment and its modification will be described.

  FIG. 11 is a block diagram illustrating a first configuration example of a data write current and magnetic field cancel current supply system according to the third embodiment.

  Referring to FIG. 11, in the configuration according to the third embodiment, memory array 10 is divided into a plurality of banks BK1, BK2,... Along the row direction. In the following, the banks BK1, BK2,... Are collectively referred to as a bank BK.

  Each bank BK has the same configuration as memory block MB shown in the first and second embodiments. Alternatively, each of the plurality of memory blocks MB configuring the memory array 10 may be divided into a plurality of banks BK. Each of the plurality of banks adjacent in the column direction can be set as a data write target at the same time. For example, in each bank BK, it is possible to select one memory cell row and execute data writing.

  In the configuration according to the third embodiment, SD drive circuits 140 and 140 #, sub-decode signal lines SD0 to SD3, current source circuits 111 and 111 #, current lines 113 and 113 #, ground lines GL and GL #, and ground node 114 114 # are shared between a plurality of banks adjacent to each other in the column direction. In the following, these circuits / wiring groups for supplying the data write current and the magnetic field canceling current to the memory array 10 are collectively referred to as a “write power supply system”. Since the arrangement of the write power supply system in FIG. 11 is the same as that shown in FIG. 4, detailed description will not be repeated.

  That is, subdecode signal lines SD0 to SD3, current lines 113 and 113 #, and ground lines GL and GL # are arranged so as to be shared among a plurality of banks along the column direction. SD drive circuits 140 and 140 #, current source circuits 111 and 111 #, and ground nodes 114 and 114 # are arranged on one side of two regions adjacent to memory array 10 in the column direction.

  Thus, in the configuration according to the third embodiment, a common write power supply system is used to supply a data write current to a plurality of write word lines WWL and to the adjacent rows corresponding thereto. A magnetic field canceling current can be supplied. Therefore, the supply of the data write current and the magnetic field canceling current to the plurality of banks can be efficiently performed while enjoying the same effect as the configuration shown in FIG.

  FIG. 12 is a block diagram illustrating a second configuration example of the data write current and magnetic field cancel current supply system according to the third embodiment.

  Referring to FIG. 12, the second configuration example of the third embodiment differs from the first configuration example shown in FIG. 11 in the arrangement of the write power supply system. That is, the write power supply system is arranged in the same manner as in FIG. 5 and is shared between a plurality of banks adjacent to each other in the column direction. Since the configuration of other parts is the same as that of FIG. 11, detailed description will not be repeated.

  Therefore, in the configuration shown in FIG. 12, the supply of the data write current and the magnetic field canceling current to the plurality of banks can be efficiently performed with the same effect as the configuration shown in FIG.

  FIG. 13 is a block diagram illustrating a third configuration example of the data write current and magnetic field cancel current supply system according to the third embodiment.

  Referring to FIG. 13, the third configuration example of the third embodiment is different in the arrangement of the write power supply system from the first configuration example shown in FIG. That is, the write power supply system is arranged in the same manner as in FIG. 6 and is shared among a plurality of banks adjacent to each other in the column direction. Since the configuration of other parts is the same as that of FIG. 11, detailed description will not be repeated.

  Therefore, in the configuration shown in FIG. 13, the supply of the data write current and the magnetic field canceling current to the plurality of banks can be efficiently performed with the same effect as the configuration shown in FIG.

  FIG. 14 is a block diagram illustrating a fourth configuration example of the data write current and magnetic field cancel current supply system according to the third embodiment.

  Referring to FIG. 14, the fourth configuration example according to the third embodiment is different from the first configuration example shown in FIG. 11 in place of each of write drive circuits WWDj0 to WWDj3. And 132, the current source circuits 110 and 110 # instead of the SD drive circuits 140 and 140 #, and the current wirings 112 and 112 # newly provided, the data write current Is different from that supplied. Since these differences are similar to the differences between FIG. 4 and FIG. 7 already described, detailed description will not be repeated.

  In the configuration shown in FIG. 14, the write power supply system includes current source circuits 110 and 110 #, current source circuits 111 and 111 #, current lines 112 and 112 #, current lines 113 and 113 #, and ground lines GL and GL #. Consists of. The write power supply system is arranged in the same manner as in FIG. 7 and is shared among a plurality of banks adjacent to each other in the column direction. Since the configuration of other parts is the same as that of FIG. 11, detailed description will not be repeated.

  Therefore, in the configuration shown in FIG. 14, the supply of the data write current and the magnetic field canceling current to the plurality of banks can be efficiently performed with the same effect as the configuration shown in FIG.

  FIG. 15 is a block diagram illustrating a fifth configuration example of the data write current and magnetic field cancel current supply system according to the third embodiment.

  Referring to FIG. 15, the fifth configuration example of the third embodiment is different in the arrangement of the write power supply system from the fourth configuration example shown in FIG. The write power supply system is arranged in the same manner as in FIG. 9, and is shared between a plurality of banks adjacent to each other in the column direction. Since the configuration of other parts is the same as that of FIG. 14, detailed description will not be repeated.

  Therefore, in the configuration shown in FIG. 15, the supply of the data write current and the magnetic field canceling current to the plurality of banks can be efficiently performed with the same effect as the configuration shown in FIG.

  FIG. 16 is a block diagram illustrating a sixth configuration example of the data write current and magnetic field cancel current supply system according to the third embodiment.

  Referring to FIG. 16, the sixth configuration example of the third embodiment is different from the fourth configuration example shown in FIG. 14 in the arrangement of the write power supply system. The write power supply system is arranged in the same manner as in FIG. 10 and is shared between a plurality of banks adjacent to each other in the column direction. Since the configuration of other parts is the same as that of FIG. 14, detailed description will not be repeated.

  Therefore, in the configuration shown in FIG. 16, the supply of the data write current and the magnetic field canceling current to the plurality of banks can be efficiently performed with the same effect as the configuration shown in FIG.

  As described above, according to the configuration according to the third embodiment, the memory array can be configured by sharing a common data write current supply system among a plurality of banks that can simultaneously execute the data write operation. Therefore, the magnetic noise can be suppressed and the data write current and magnetic field cancel current can be made uniform to stabilize the data write operation.

[Embodiment 4]
In the fourth embodiment, a configuration of a write drive circuit that can be efficiently arranged in a small area will be described.

  FIG. 17 is a circuit diagram showing a configuration example of a write drive circuit according to the fourth embodiment. Also in the configuration according to the fourth embodiment, it is assumed that hierarchical row selection is performed by the main word line MWL and the write word line WWL as in the first embodiment.

  Referring to FIG. 17, one end of each write word line WWL is connected to power supply voltage Vcc regardless of the row selection result, and the other end is connected to ground voltage via driver transistors DTN1 and DTN2 formed of N channel MOS transistors. Connected to Vss. Similarly to the write drive circuit WWD shown in the first embodiment, the driver transistors DTN1 and DTN2 are alternately arranged for each row.

  That is, in the even-numbered write word lines WWLj0 and WWLj1, the driver transistors DTN1 and DTN2 are arranged between one end on the side closer to the row selection circuit 20 and the ground voltage Vss, and the other end on the side far from the row selection circuit 20 is connected. The power supply voltage Vcc is connected. On the other hand, in odd-numbered write word lines WWLj2 and WWLj3, one end on the side closer to the row selection circuit 20 is connected to the power supply voltage Vcc, and between the other end on the side far from the row selection circuit 20 and the ground voltage Vss. Driver transistors DTN1 and DTN2 are arranged in the circuit. Driver transistors DTN1 and DTN2 are designed to have current drivability corresponding to data write current Iww and magnetic field cancel current ΔIww, respectively.

  Driver transistors DTN1 and DTN2 have their gates connected to nodes N1 and N2, respectively. The voltages at the nodes N1 and N2 are controlled by the selection circuit 250. FIG. 17 illustrates the configuration of the selection circuit corresponding to the even-numbered write word lines WWLj0 and WWLj1.

  The selection circuit 250 includes logic gates 251a and 251b and logic circuits 252a and 252b. Logic gate 251a outputs the AND logic operation result of voltage level of main word line MWLj and subdecode signal SD0 to node N1. The logic circuit 252a outputs an AND logic operation result of the voltage level of the main word line MWLj and the subdecode signal SD2, and an AND gate outputs an AND logic operation result of the voltage level of the main word line MWLj and the subdecode signal SD3. A gate, and an OR gate that outputs an OR logical operation result of outputs of the two AND gates to the node N2.

  Similarly, logic gate 251b outputs an AND logic operation result of the voltage level of main word line MWLj and subdecode signal SD1 to node N1. The logic circuit 252b outputs an AND gate that outputs an AND logic operation result of the voltage level of the main word line MWLj + 1 and the sub-decode signal SD2, and outputs an AND logic operation result of the voltage level of the main word line MWLj and the sub-decode signal SD3. And an OR gate that outputs an OR logical operation result of the outputs of the two AND gates to the node N2.

  Thus, in each memory cell row, node N1 is set to H level when the row is selected, and is set to L level otherwise, and node N2 is adjacent to the row. When H is selected, it is set to H level, and otherwise it is set to L level.

  As a result, the data write current Iww flows in the direction from the power supply voltage Vcc to the ground voltage Vss by the turned-on driver transistor DTN1 in the write word line WWL of the selected row. Further, in the write word line WWL in the adjacent row, the magnetic field canceling current ΔIww flows in the opposite direction to the write word line in the selected row by the turned-on driver transistor DTN2.

  If the row is neither a selected row nor an adjacent row, both nodes N1 and N2 are set to L level, so that both driver transistors DTN1 and DTN2 are turned off, and write word line WWL The voltage is fixed at Vcc.

  By adopting such a configuration, it is possible to generate a canceling magnetic field as in the first embodiment, and to suppress magnetic disturbance to unselected memory cells due to data write current flowing through the write word line of the selected row. Become.

  Furthermore, since the driver transistor is configured by an N channel MOS transistor having a higher current driving capability per unit size than the P channel MOS transistor, the area of the write drive circuit can be reduced.

FIG. 18 is a circuit diagram showing another configuration example of the write drive circuit according to the fourth embodiment.
The write drive circuit shown in FIG. 18 is different from the write drive circuit shown in FIG. 17 in that data write current Iww is supplied by the sum of the passing currents of driver transistors DTN1 and DTN2.

  In other words, selection circuit 250 # arranged in place of selection circuit 250 shown in FIG. 17 adds OR of outputs of logic gate 251a and logic circuit 252a in each memory cell row in addition to the configuration of selection circuit 250. It further has a logic gate for outputting the operation result to the node N2. FIG. 18 representatively shows logic gates 253a and 253b corresponding to write word lines WWLj0 and WWLj1 among these logic circuits.

  Therefore, in each memory cell row, node N1 is set to H level when the row is selected, while node N2 is set to H level when the row corresponds to either the selected row or an adjacent row. Is set.

  As a result, in each memory cell row, when the row is selected, both of the driver transistors DTN1 and DTN2 are turned on. When the row is an adjacent row, only the driver transistor DTN2 is turned on. If it is neither the selected row nor the adjacent row, both driver transistors DTN1 and DTN2 are turned off.

  In other words, the current driving capability of driver transistors DTN1 and DTN2 is set similarly to driver transistors 101 (101 #) and driver transistors 102 (102 #) in write drive circuit WWD shown in FIG. As a result, in the configuration shown in FIG. 18, the current driving capability of the driver transistor DTN1, that is, the transistor size can be reduced as compared with the configuration shown in FIG. 17, so that the write drive circuit can be further miniaturized. it can.

[Modification of Embodiment 4]
In the modification of the fourth embodiment, a configuration of a write drive circuit suitable for a small memorial configuration will be described.

  FIG. 19 is a circuit diagram showing a configuration example of a write drive circuit according to a modification of the fourth embodiment.

  Referring to FIG. 19, in the configuration according to the modification of the fourth embodiment, driver transistors DTN1 and DTN2 or driver transistors DTP1 and DTP2 are provided on one end side (side closer to row selection circuit 20) of each write word line WWL. Any one of them is arranged, and the other end side (the side far from the row selection circuit 20) of each write word line WWL is connected to the ground voltage Vss or the power supply voltage Vcc.

  For example, even-numbered write word lines (for example, WWLj0, WWLj1) are connected at one end to ground voltage Vss via driver transistors DTN1 and DTN2 formed of N-channel MOS transistors, and at the other end are row-selected. Regardless of the result, the power supply voltage Vcc is fixedly connected. Driver transistors DTN1 and DTN2 are designed to have current drivability corresponding to data write current Iww and magnetic field cancel current ΔIww, respectively.

  In contrast, odd-numbered write word lines (for example, WWLj2, WWLj3) are connected at one end to power supply voltage Vcc via driver transistors DTP1, DTP2 formed of P-channel MOS transistors and at the other end. Regardless of the row selection result, it is fixedly coupled to ground voltage Vss. Driver transistors DTP1 and DTP2 are designed to have current driving capabilities corresponding to data write current Iww and magnetic field cancel current ΔIww, respectively.

  The gates of driver transistors DTN1 and DTN2 are connected to nodes N1 and N2, respectively, and the gates of driver transistors DTP1 and DTP2 are connected to nodes / N1 and / N2, respectively.

  Select circuit 260 controls the voltage level of nodes N1, N2 or nodes / N1, / N2 in each memory cell row in accordance with subdecode signals SD0-SD3 and the voltage level of main word line MWL.

  FIG. 19 typically shows a circuit configuration corresponding to write word lines WWLj0 and WWLj3.

  The selection circuit 260 includes logic gates 261a and 261b and logic circuits 262a and 262b. Logic gate 261a outputs an AND logic operation result of the voltage level of main word line MWLj and subdecode signal SD0 to node N1. Logic circuit 262a outputs an AND gate that outputs an AND logic operation result of the voltage level of main word line MWLj and subdecode signal SD2, and outputs an AND logic operation result of the voltage level of main word line MWLj and subdecode signal SD3. And an OR gate that outputs an OR logical operation result of the outputs of the two AND gates to the node N2.

  Similarly, logic gate 261b outputs the NAND logic operation result of the voltage level of main word line MWLj and subdecode signal SD3 to node / N1. The logic circuit 262b outputs an AND logic operation result that outputs an AND logic operation result between the voltage level of the main word line MWLj and the subdecode signal SD0, and outputs an AND logic operation result between the voltage level of the main word line MWLj and the subdecode signal SD1. And an NOR gate that outputs a NOR logic operation result of each output of the two AND gates to the node / N2.

  As a result, in the memory cell row (for example, even row) where driver transistors DTN1 and DTN2 are arranged, node N1 is set to H level when the row is selected, and is set to L level in other cases. Node N2 is set to H level when an adjacent row is selected, and is set to L level in other cases.

  In contrast, in a memory cell row (for example, odd row) in which driver transistors DTP1 and DTP2 are arranged, node / N1 is set to L level when the row is selected, and is set to H level otherwise. The Node / N2 is set to L level when the row is an adjacent row, and is set to H level in other cases.

  By adopting such a configuration, similarly to the configuration shown in FIG. 17, the data write current Iww can be supplied to the selected row and the magnetic field canceling current ΔIww in the opposite direction can be supplied to the adjacent row.

  Furthermore, since driver transistors can be arranged on one side of the memory array 10 in each memory cell row, it is not necessary to arrange the selection circuits 260 at both ends, and the circuit area of the row selection circuit can be reduced. . In particular, in a small-scale memory array configuration in which the necessity of dividing the memory array 10 into a plurality of memory blocks along the column direction is small, the driver transistor group can be efficiently formed by adopting such a write driver configuration. It becomes possible to arrange.

  FIG. 20 is a circuit diagram showing another configuration example of the write drive circuit according to the modification of the fourth embodiment.

  The write drive circuit shown in FIG. 20 is different from the write drive circuit shown in FIG. 19 in that data write current Iww is supplied by the sum of the passing currents of driver transistors DTN1 and DTN2 or driver transistors DTP1 and DTP2. Different.

  That is, selection circuit 260 # arranged in place of selection circuit 260 shown in FIG. 19 includes logic gate 261a in each of the memory cell rows in which driver transistors DTN1 and DTN2 are arranged in addition to the configuration of selection circuit 260. And a logic gate that outputs an OR operation result of the outputs of the logic circuits 262a to the node N2, and in each of the memory cell rows in which the driver transistors DTP1 and DTP2 are arranged, each of the logic gates 261b and the logic circuits 262b And a logic gate for outputting the AND operation result of the output of the output to node / N2. In FIG. 20, among these logic gates, logic gates 263a and 263b corresponding to write word lines WWLj0 and WWLj3 are representatively shown.

  Therefore, in each memory cell row, node N1 is set to H level when the row is selected, while node N2 is set to H level when the row corresponds to either the selected row or an adjacent row. Is set. Similarly, node / N1 is set to L level when the row is selected, while node / N2 is set to L level when the row corresponds to either the selected row or an adjacent row. .

  As a result, in each memory cell row, when the row is selected, both driver transistors DTN1 and DTN2 or DTP1 and DTP2 are turned on. When the row is an adjacent row, only driver transistor DTN2 or DTP2 is turned on. Turn on. On the other hand, when the row is neither a selected row nor an adjacent row, driver transistors DTN1 and DTN2 or DTP1 and DTP2 are turned off.

  In other words, the current driving capability of driver transistors DTN1 and DTN2 is set similarly to driver transistors 101 (101 #) and driver transistors 102 (102 #) in write drive circuit WWD shown in FIG. Similarly, the current driving capabilities of the driver transistors DTP1 and DTP2 are set in the same manner as described above.

  As a result, in the configuration shown in FIG. 20, the current driving power of the driver transistors DTN1 and DTP1, that is, the transistor size can be reduced as compared with the configuration shown in FIG. 19, thereby further reducing the size of the write drive circuit. be able to.

[Embodiment 5]
In the fifth embodiment, the equalization of the current path length mentioned in the second embodiment and its modification will be described by extracting only the configuration corresponding to the data write current.

  FIG. 21 is a block diagram illustrating a first configuration example of a data write current supply system according to the fifth embodiment.

  Referring to FIG. 21, also in the configuration according to the fifth embodiment, write drive circuits 131 are alternately arranged for each row corresponding to one of both ends of each write word line WWL. The other of both ends of each write word line WWL is connected to ground nodes 114 and 114 # that supply ground voltage Vss via ground lines GL and GL #. Thus, in order to supply data write current Iww to write word line WWL arranged along the row direction, current lines 112 and 112 # and ground lines GL and GL # are arranged along the column direction. Is arranged.

  The data write current Iww is supplied to the write drive circuit 131 corresponding to the even row by the current source circuit 110 and the current wiring 112, and the data write current Iww that has passed through the write word line is connected to the ground node 114 by the ground wiring GL. Led to.

  Write drive circuit 131 corresponding to the odd row is supplied with data write current Iww by current source circuit 110 # and current line 112 #, and data write current Iww that has passed through the write word line is supplied by ground line GL #. Guided to ground node 114 #.

  At this time, current source circuit 110 (110 #) generating data write current Iww and ground node 114 (114 #) acting as a sink of data write current Iww are opposite to each other across memory array 10. By arranging in the region on the side, the current path length of data write current Iww can be kept constant regardless of the position of the selected memory cell row.

  Furthermore, the electrical resistance value per unit length is similarly designed for each of current lines 112 and 112 # and ground lines GL and GL #. As a result, the amount of data write current Iww can be made uniform regardless of the selected position of the memory cell row, the data write characteristics in memory array 10 are made uniform, and the data write margin is increased. It can be secured.

  FIG. 21 shows a configuration in which the write drive circuits 131 are alternately arranged for each row in order to efficiently arrange the write drive circuits 131. However, the write drive circuits 131 are arranged corresponding to only one side of the write word line WWL. Even in this case, it is possible to obtain the same effect by arranging the current source circuit 110 and the ground node 114 in opposite regions.

  FIG. 22 is a block diagram illustrating a second configuration example of the data write current supply system according to the fifth embodiment.

  In the configuration shown in FIG. 22, in addition to the first configuration example shown in FIG. 21, current source circuit 110 or 110 # is arranged corresponding to both ends of current lines 112 and 112 #, respectively. Also, ground node 114 or 114 # is arranged corresponding to both ends of ground lines GL and GL #, respectively. Since the configuration of other parts is the same as that of FIG. 21, detailed description will not be repeated.

  By adopting such a configuration, in addition to the same effect as the configuration shown in FIG. 21, the effective current path length of the data write current Iww can be shortened, so that the power consumption during data writing can be reduced. Further efforts are possible.

[Modification of Embodiment 5]
In the modification of the fifth embodiment, a configuration in the case where the data write current configuration shown in the fifth embodiment is provided to a memory array divided into a plurality of banks will be described.

  FIG. 23 is a block diagram illustrating a first configuration example of a data write current supply system according to a modification of the fifth embodiment.

  Referring to FIG. 23, in the modification of the fifth embodiment, memory array 10 is divided into a plurality of banks BK along the row direction as in the third embodiment. Since the configuration and operation of each bank BK are the same as those described in the third embodiment, detailed description will not be repeated.

  Even in the configuration according to the modification of the fifth embodiment, the write power supply system configured by current source circuits 110 and 110 #, current lines 112 and 112 #, ground lines GL and GL #, and ground nodes 114 and 114 # Shared among a plurality of banks adjacent to each other in the column direction. Since the arrangement of the write power supply system in FIG. 23 is the same as that shown in FIG. 21, detailed description will not be repeated.

  As described above, in the configuration shown in FIG. 23, a data write current can be supplied to a plurality of write word lines WWL using a common write power supply system. Therefore, the supply of the data write current to the plurality of banks can be efficiently performed while enjoying the same effect as the configuration shown in FIG.

  FIG. 24 is a block diagram illustrating a second configuration example of the data write current supply system according to the modification of the fifth embodiment.

  Referring to FIG. 24, the second configuration example of the modification of the fifth embodiment is different in the arrangement of the write power supply system from the first configuration example shown in FIG. That is, the write power supply system is arranged in the same manner as in FIG. 22, and is shared between a plurality of banks adjacent to each other in the column direction. Since the configuration of other parts is the same as that of FIG. 23, detailed description will not be repeated.

  Therefore, in the configuration shown in FIG. 24, the supply of the data write current to a plurality of banks can be efficiently performed with the same effect as the configuration shown in FIG.

  As described above, according to the configuration according to the modification of the fifth embodiment, data writing in memory array 10 can be performed by a common write power supply system among a plurality of banks that can simultaneously execute data writing operations. It becomes possible to secure a data writing margin with uniform characteristics.

  In the fifth embodiment and its modification, the configuration for keeping the path length of the data write current supplied to write word line WWL constant has been described, but the same configuration is supplied to bit line BL. It is also possible to apply to the data write current path to be performed.

  In this case, the bit line drive circuits BDVa and BDVb shown in FIG. 2 are arranged at both ends of each of the bit lines BL arranged along the column direction. Accordingly, current lines 112 and 112 # and ground lines GL and GL # in the configurations of FIGS. 21 to 24 are arranged along the row direction to guide the data write current to bit line drive circuits BDVa and BDVb. To do. Furthermore, current source circuits 110 and 110 # and ground nodes 114 and 114 # are arranged in the same manner as in FIGS. 21 to 24, corresponding to the ends of current lines 112 and 112 # and ground lines GL and GL #. Thus, the data write current can be made uniform regardless of the selected position of the memory cell column.

  In the first to fifth embodiments and their modifications, the case where the current supply to the write word line WWL is controlled by the hierarchical configuration with the main word line MWL is shown. It is not limited to such a configuration. That is, each write drive circuit may be controlled according to a row decode signal provided corresponding to each memory cell row, instead of the main word line and the sub decode signal. Also in this case, the same effect can be obtained by modifying the configuration of the decoding circuit so that the control of the write drive circuit (driver transistor) in the row and the adjacent row is the same as in the above configuration example. it can.

[Embodiment 6]
In the sixth embodiment, a configuration for preventing erroneous data writing due to magnetic noise from wiring (hereinafter also referred to as “peripheral wiring”) arranged outside the memory array 10 will be described.

FIG. 25 is a block diagram illustrating arrangement of peripheral wirings according to the sixth embodiment.
Referring to FIG. 25, peripheral wiring 270 is arranged in the peripheral region of memory array 10 and is the wiring closest to the end write word line WWLn. As already described, a data write current Iww in a fixed direction flows through write word line WWLn for generating a data write magnetic field along the hard axis direction when a corresponding memory cell row is selected.

  On the other hand, the peripheral wiring 270 is provided to supply the power supply voltage Vcc to the internal circuit 280, and the operating current Ic of the internal circuit 280 flows through the peripheral wiring 270. In such a peripheral wiring 270, (1) the operating current Ic does not flow at the supply timing of the data write current Iww, that is, the supply periods of the data write current and the operating current do not overlap, or (2) When the supply timings of the data write current Iww and the operation current Ic overlap, they are selected so as to satisfy at least one of the two conditions that the directions of the operation current Ic and the data write current Iww are opposite to each other. .

  In order to indicate the condition (1), for example, the power supply wiring for the internal circuit 280 of the data reading system that operates at the time of data reading can be arranged as the peripheral wiring 270 in the vicinity of the memory array 10.

  Alternatively, as shown in FIG. 26, the ground wiring for supplying the ground voltage Vss (GND) to the internal circuit 280 can be arranged as the peripheral wiring 270 closest to the endmost write word line WWLn. is there. In this case, the current Ig flows through the peripheral wiring 270 in accordance with the operation timing of the internal circuit 280.

  With such a configuration, no magnetic noise is applied from the peripheral wiring 270 to the memory array 10 during data writing.

  Further, as shown in FIG. 27, the peripheral wiring 270 can be applied as the current wiring 112 shown in FIG. That is, the current Ic passing through the peripheral wiring 270 (current wiring 112) is equal to the data write current Iww supplied to the write word line WWL via the write drive circuit 131 arranged in the write driver band 21. .

  Therefore, current wiring 112 is arranged as peripheral wiring 270 along the same direction as write word line WWL, and one end side and the other end side thereof are connected to power supply voltage Vcc and write drive circuit 131, respectively. The currents flowing through the peripheral wiring 270 (current wiring 112) and the write word line WWLn can be set to have the same strength and in the opposite directions.

  As a result, in the other non-selected memory cells corresponding to the write word lines other than the write word line WWLn, the data write current Iww flowing through the write word line WWLn and the operating current Ic flowing through the current wiring 112 (peripheral wiring 270). Since the generated magnetic fields weaken each other, the risk of erroneous data writing due to magnetic noise from the peripheral wiring 270 can be reduced.

  As described above, the condition of the peripheral wiring 270 can be realized by selecting the connection destination (internal circuit 280) of the peripheral wiring 270 and designing the positional relationship between the connection destination and the peripheral wiring 270.

  With such a configuration, it is possible to suppress the risk of erroneous data writing in the memory array 10 due to magnetic noise caused by the current flowing through the peripheral wiring 270 adjacent to the outermost write word line WWLn.

  The same selection of the peripheral wiring can be similarly applied to the peripheral wiring provided in the upper region or the lower region of the memory array 10.

  28 and 29 show peripheral wirings 272 and 273 closest to the write word line WWLi (i: natural number) in the upper region or the lower region of the memory array 10. The peripheral wiring 272 shown in FIG. 28 supplies the power supply voltage Vcc to the internal circuit 280, and the peripheral wiring 273 shown in FIG. 29 supplies the ground voltage Vss to the internal circuit 280. Yes.

  In such a configuration, as described above, by selecting the circuit that does not operate during data writing or the write drive circuit 131 that supplies the data write current to the write word line WWLi as the internal circuit 280, as shown in FIG. The same effect as that of the peripheral wiring 270 shown in FIG. 27 can be obtained.

[Modification of Embodiment 6]
In the modification of the sixth embodiment, the arrangement of peripheral wirings close to the bit line BL to which a current in a different direction is supplied according to the write data level will be described.

  FIG. 30 is a first block diagram illustrating an example of the arrangement of peripheral wiring in a modification of the sixth embodiment.

  Referring to FIG. 30, peripheral wiring 275 is arranged in the peripheral region of memory array 10 and is the wiring closest to the outermost bit line BLm. As already explained, the bit line BLm for generating the data write magnetic field along the easy axis direction has a data write current + Iwb according to the level of the write data when the corresponding memory cell column is selected. Either -Iwb is flowed.

  The peripheral wiring 275 is also arranged so that one of the conditions (1) and (2) regarding the peripheral wiring 270 described in FIG. 25 is satisfied.

  Therefore, as shown in FIG. 30, by making internal circuit 285 a data read system circuit that does not operate at the time of data writing, magnetic noise is generated from peripheral wiring 275 closest to memory array 10 at the time of data writing. It is possible to avoid acting on the memory array 10.

  Alternatively, the current wiring for supplying the operating current to the bit line drive circuits BDVa and BDVb shown in FIG. 2 can be applied as the peripheral wiring close to the bit line BL.

  Referring to FIG. 31, as described in FIG. 2, bit line drive circuits BDVa and BDVb are arranged at both ends of each bit line. In the peripheral region of memory array 10, current wires 277a and 277b are arranged as peripheral wires closest to the outermost bit line BLm. Current lines 277a and 277b are arranged along the same direction as bit line BL. The current line 277a has one end connected to the power supply voltage Vcc and the other end connected to each of the bit line drive circuits BDVa. Similarly, the current line 277b has one end connected to the power supply voltage Vcc and the other end connected to each of the bit line drive circuits BDVb.

  With this arrangement, the data write currents + Iwb and -Iwb are caused to flow so that the current lines 277a and 277b and the bit line of the selected column are turned back by the bit line drive circuits BDVa and BDVb. As a result, for example, when data write current + Iwb is caused to flow through the outermost bit line BLm, an operation current Ic in the opposite direction is caused to flow through the current line 277a, and data write to the outermost bit line BLm. When the sink current -Iwb is supplied, the operating current Ic 'in the opposite direction is supplied to the current line 277b.

  Thereby, in the peripheral region of the memory array 10, the directions of currents passing through the outermost bit line BLm and the nearest peripheral wiring can be set in opposite directions. As a result, since the condition (2) described above is satisfied, it is possible to suppress the adverse effect of magnetic noise acting on the memory array 10 from the peripheral wiring at the time of data writing.

  Further, with respect to the peripheral wiring provided in the same direction as the bit line BL, the same arrangement rule as in FIGS. 30 and 31 can be applied to the peripheral wiring provided in the upper region or the lower region of the memory array 10.

  32 and 33 show peripheral wirings 275 and 278 that are closest to the bit line BLj (j: natural number) in the upper region or the lower region of the memory array 10, respectively. The peripheral wiring 275 shown in FIG. 32 supplies the power supply voltage Vcc to the internal circuit 285, and the peripheral wiring 278 shown in FIG. 33 supplies the ground voltage Vss to the internal circuit 285. Yes.

  In such a configuration, as described above, as the internal circuit 285, the circuit that does not operate at the time of data writing and the bit line drive circuits BDVa and BDVb are arranged, and thus the same as the peripheral wiring shown in FIG. 30 and FIG. The effect of can be obtained.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating supply of a data write current according to the first embodiment. FIG. 10 is a circuit diagram illustrating supply of a data write current according to a modification of the first embodiment. FIG. 11 is a block diagram illustrating a first configuration example of a data write current and magnetic field cancel current supply system according to the second embodiment. FIG. 11 is a block diagram illustrating a second configuration example of a data write current and magnetic field cancel current supply system according to the second embodiment. FIG. 12 is a block diagram illustrating a third configuration example of a data write current and magnetic field cancel current supply system according to the second embodiment. FIG. 12 is a block diagram illustrating a first configuration example of a data write current and magnetic field cancellation current supply system according to a modification of the second embodiment. FIG. 8 is a circuit diagram showing a configuration of a write drive circuit shown in FIG. 7. FIG. 12 is a block diagram illustrating a second configuration example of a data write current and magnetic field cancellation current supply system according to a modification of the second embodiment. FIG. 11 is a block diagram illustrating a third configuration example of a data write current and magnetic field cancellation current supply system according to a modification of the second embodiment. FIG. 10 is a block diagram illustrating a first configuration example of a data write current and magnetic field cancel current supply system according to a third embodiment. FIG. 12 is a block diagram illustrating a second configuration example of a data write current and magnetic field cancel current supply system according to the third embodiment. FIG. 11 is a block diagram illustrating a third configuration example of a data write current and magnetic field cancel current supply system according to the third embodiment. FIG. 11 is a block diagram illustrating a fourth configuration example of a data write current and magnetic field cancel current supply system according to the third embodiment. FIG. 10 is a block diagram illustrating a fifth configuration example of a data write current and magnetic field cancel current supply system according to a third embodiment. It is a block diagram explaining the 6th structural example of the supply system of the data write current and magnetic field cancellation current according to Embodiment 3. FIG. 10 is a circuit diagram showing a configuration example of a write drive circuit according to a fourth embodiment. FIG. 14 is a circuit diagram showing another configuration example of the write drive circuit according to the fourth embodiment. FIG. 16 is a circuit diagram showing a configuration example of a write drive circuit according to a modification of the fourth embodiment. FIG. 22 is a circuit diagram showing another configuration example of the write drive circuit according to a modification of the fourth embodiment. FIG. 17 is a block diagram illustrating a first configuration example of a data write current supply system according to a fifth embodiment. FIG. 17 is a block diagram illustrating a second configuration example of a data write current supply system according to the fifth embodiment. FIG. 29 is a block diagram illustrating a first configuration example of a data write current supply system according to a modification of the fifth embodiment. FIG. 29 is a block diagram illustrating a second configuration example of a data write current supply system according to a modification of the fifth embodiment. FIG. 20 is a first block diagram illustrating arrangement of peripheral wirings according to a sixth embodiment. FIG. 23 is a second block diagram illustrating the arrangement of peripheral wirings according to the sixth embodiment. FIG. 23 is a third block diagram for explaining the arrangement of peripheral wirings according to the sixth embodiment. FIG. 14 is a fourth block diagram for explaining the arrangement of peripheral wirings according to the sixth embodiment. FIG. 23 is a fifth block diagram for explaining the arrangement of peripheral wirings according to the sixth embodiment. FIG. 28 is a first block diagram illustrating the arrangement of peripheral wirings according to a modification of the sixth embodiment. FIG. 25 is a second block diagram illustrating the arrangement of peripheral wiring according to a modification of the sixth embodiment. FIG. 25 is a third block diagram for explaining the arrangement of peripheral wirings according to a modification of the sixth embodiment. FIG. 25 is a fourth block diagram for explaining the arrangement of peripheral wirings according to a modification of the sixth embodiment. It is the schematic which shows the structure of an MTJ memory cell. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram for demonstrating the magnetization state of the tunnel magnetoresistive element at the time of the data writing with respect to an MTJ memory cell.

Explanation of symbols

  1 MRAM device, 10 memory array, 20 row selection circuit, 30 column selection circuit, 50, 60 read / write control circuit, 51, 61 bit line drive unit, 101, 102, 101 #, 102 #, 102d, 103d, DTn1, DTN2, DTP1, DTP2 driver transistor, 110, 110 #, 111, 111 # current source circuit, 112, 112 #, 113, 113 # current wiring, 114, 114 # ground node, 131, 132, WWD write drive circuit 270,272,273,275,278 peripheral wiring, 280,285 internal circuit, ADD address signal, ATR access transistor, BDVa, BDVb bit line drive circuit, BK bank, BL bit line, DRWL dummy read word line, DWWL dummy line Word line, GL, GL # ground wiring, Iww data write current, MB memory block, MC MTJ memory cell, MWL main word line, RWL read word line, SD1-SD3 subdecode signal (signal line), TMR tunnel magnetoresistance Element, Vcc power supply voltage, Vss ground voltage, WWD write drive circuit, WWDd dummy write drive circuit, WWL write word line, ΔIww magnetic field cancellation current.

Claims (7)

A memory array in which a plurality of magnetic memory cells each having a magnetic material magnetized in a direction according to stored data are arranged in a matrix;
A plurality of write current wirings selectively receiving supply of a data write current to selectively apply a data write magnetic field to a part of the plurality of memory cells;
Outside the memory array, the peripheral wiring arranged along the same direction as the plurality of write current wiring,
The thin film magnetic memory device, wherein a current flowing through the peripheral wiring and a current flowing through a write current wiring closest to the peripheral wiring among the plurality of write current wirings are in directions opposite to each other. A plurality of write current drive circuits provided corresponding to the plurality of write current wirings, respectively;
2. The thin film magnetic device according to claim 1, wherein the peripheral wiring is connected to one of the plurality of write current driving circuits corresponding to the closest write current wiring to pass the data write current. Body storage device. A memory array in which a plurality of magnetic memory cells each having a magnetic material magnetized in a direction according to stored data are arranged in a matrix;
A plurality of write current wirings selectively receiving supply of a data write current to selectively apply a data write magnetic field to a part of the plurality of memory cells;
Outside the memory array, the peripheral wiring arranged along the same direction as the plurality of write current wiring,
The connection destination of the peripheral wiring is a thin film magnetic memory device designed so that a period during which the data write current flows and a period during which the current flows through the peripheral wiring do not overlap each other.   The plurality of write current wirings receive the data write current in a predetermined direction, and cause a magnetic field along the hard axis to act on the part of the plurality of memory cells. The thin film magnetic memory device described.   The plurality of write current wirings receive the data write current in a direction corresponding to write data, and act a magnetic field along an easy axis on the part of the plurality of memory cells. Item 4. The thin film magnetic memory device according to Item 1 or 3.   The thin film magnetic memory device according to claim 1, wherein the peripheral wiring is disposed in a peripheral region of the memory array.   4. The thin film magnetic memory device according to claim 1, wherein the peripheral wiring is arranged in one of an upper region and a lower region of the memory array.

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