JPS58174759U - 2 out of 3 redundant circuit system - Google Patents
2 out of 3 redundant circuit systemInfo
- Publication number
- JPS58174759U JPS58174759U JP7108782U JP7108782U JPS58174759U JP S58174759 U JPS58174759 U JP S58174759U JP 7108782 U JP7108782 U JP 7108782U JP 7108782 U JP7108782 U JP 7108782U JP S58174759 U JPS58174759 U JP S58174759U
- Authority
- JP
- Japan
- Prior art keywords
- power section
- transistor
- human power
- diode connected
- forward direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Safety Devices In Control Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の2アウト・オブ3の冗長回路方式を示す
回路図、第2図は本考案による冗長回路方式の一実施例
を示す回路図、第3図は本回路の応用例を示す図である
。
IC工〜■C3・・・・・・演算増幅器、D1〜D9・
・・・・・ダイオード、Q□〜Q6・・・・・・トラン
ジスタ、1〜3・・・・・・入力端子、4.5・・・・
・・出力端子、6・・・・・・センサ、7・・・・・・
冗長回路、8・・・・・・制御器、9.9a、 9b。
9C・・・・・・制御対象物。Figure 1 is a circuit diagram showing a conventional 2-out-of-3 redundant circuit system, Figure 2 is a circuit diagram showing an embodiment of the redundant circuit system according to the present invention, and Figure 3 is an example of application of this circuit. It is a diagram. IC engineering ~■C3...Operation amplifier, D1~D9・
...Diode, Q□~Q6...Transistor, 1-3...Input terminal, 4.5...
...Output terminal, 6...Sensor, 7...
Redundant circuit, 8...Controller, 9.9a, 9b. 9C... Controlled object.
Claims (1)
、第2、第3の検出器と、2個のトランジスタを縦続接
続した第1、第2、第3のトランジスタ縦接回路を並列
接続して成り、第1、第2のトランジスタ縦続回路のそ
れぞれ一方のトランジスタのベース間を接続した第1人
力部、第1のトランジスタ縦続回路の他方のトランジス
タのベースと第3のトランジスタ縦続回路の一方のトラ
ンジスタのベース間を接続した第2人力部および第2の
トランジスタ縦続回路の他方のトランジスタのベースと
第3のトランジスタ縦続回路の他方のベース間を接続し
た第3人力部を有する2アウト・オブ3回路と、前記第
1の検出器出力と前記第1人力部間に逆方向に接続され
た第1のダイオードと、前記第2の検出器出力と前記第
1人力部に順方向に接続された第2のダイオードと、第
3の検出器出力と前記第1人力部間に順方向に接続され
た第3のダイオードと、前記第2の検出器出力と前記第
2人力部間に逆方向に接続された第4のダイオードと、
前記第3の検出器出力と前記第2人力部間に順方向に接
続された第5のダイオードと、前記第1の検出器出力と
前記第2人力部間に順方向に接続された第6のダイオー
ドと、前記第3の検出器と前記第3人力部間に逆方向に
接続された第7のダイオードと、前記第1の検出器と前
記第3人力部間に順方向に接続された第8のダイオード
と、前記第2の検出器出力と前記第3人力部間に順方向
に接続された第9のダイオードとから構成した2アウト
・オブ3冗長回路方式。A first circuit that receives the first, second, and third detection signals as inputs, respectively.
, second and third detectors, and first, second and third transistor cascade circuits each having two transistors connected in cascade are connected in parallel, and each of the first and second transistor cascade circuits is connected in parallel. A first power section connected between the bases of one transistor, a second power section connected between the base of the other transistor of the first transistor cascade circuit and the base of one transistor of the third transistor cascade circuit, and a 2-out-of-3 circuit having a third power section connected between the base of the other transistor of the transistor cascade circuit and the other base of the third transistor cascade circuit; and the first detector output and the first transistor cascade circuit. a first diode connected in a reverse direction between the human power section, a second diode connected in a forward direction between the second detector output and the first human power section, and a third detector output and the first diode connected in a forward direction; a third diode connected in a forward direction between the first human power section; and a fourth diode connected in a reverse direction between the second detector output and the second human power section;
a fifth diode connected in a forward direction between the third detector output and the second human power section; and a sixth diode connected in a forward direction between the first detector output and the second human power section. a seventh diode connected in a reverse direction between the third detector and the third human power section, and a seventh diode connected in the forward direction between the first detector and the third human power section. A 2-out-of-3 redundant circuit system comprising an eighth diode and a ninth diode connected in a forward direction between the second detector output and the third human power section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7108782U JPS58174759U (en) | 1982-05-14 | 1982-05-14 | 2 out of 3 redundant circuit system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7108782U JPS58174759U (en) | 1982-05-14 | 1982-05-14 | 2 out of 3 redundant circuit system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58174759U true JPS58174759U (en) | 1983-11-22 |
JPS6142190Y2 JPS6142190Y2 (en) | 1986-12-01 |
Family
ID=30080719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7108782U Granted JPS58174759U (en) | 1982-05-14 | 1982-05-14 | 2 out of 3 redundant circuit system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58174759U (en) |
-
1982
- 1982-05-14 JP JP7108782U patent/JPS58174759U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6142190Y2 (en) | 1986-12-01 |
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