JPH021927U - - Google Patents

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Publication number
JPH021927U
JPH021927U JP8080288U JP8080288U JPH021927U JP H021927 U JPH021927 U JP H021927U JP 8080288 U JP8080288 U JP 8080288U JP 8080288 U JP8080288 U JP 8080288U JP H021927 U JPH021927 U JP H021927U
Authority
JP
Japan
Prior art keywords
circuit
state
output
digital circuit
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8080288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8080288U priority Critical patent/JPH021927U/ja
Publication of JPH021927U publication Critical patent/JPH021927U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例によるデイジタル
回路の回路図、第2図は第1図の入出力端子の波
形図、第3図は従来のデイジタル回路の回路図、
第4図は第3図の入出力端子の波形図である。 図において、1は入力端子、2は出力端子、3
は出力制御用入力端子、4は可変形遅延回路を示
す。なお、図中、同一符号は同一、または相当部
分を示す。
FIG. 1 is a circuit diagram of a digital circuit according to an embodiment of this invention, FIG. 2 is a waveform diagram of the input/output terminals of FIG. 1, and FIG. 3 is a circuit diagram of a conventional digital circuit.
FIG. 4 is a waveform diagram of the input/output terminals of FIG. 3. In the figure, 1 is an input terminal, 2 is an output terminal, and 3 is an input terminal.
4 indicates an input terminal for output control, and 4 indicates a variable delay circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3ステイト出力回路をもつデイジタル回路に出
力制御用遅延回路を追加することにより3ステイ
ト状態での出力を接続される外部回路に合せて自
由に設定できるようにしたことを特徴とするデイ
ジタル回路。
A digital circuit characterized in that an output control delay circuit is added to a digital circuit having a 3-state output circuit so that the output in the 3-state state can be freely set according to a connected external circuit.
JP8080288U 1988-06-17 1988-06-17 Pending JPH021927U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8080288U JPH021927U (en) 1988-06-17 1988-06-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8080288U JPH021927U (en) 1988-06-17 1988-06-17

Publications (1)

Publication Number Publication Date
JPH021927U true JPH021927U (en) 1990-01-09

Family

ID=31305620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8080288U Pending JPH021927U (en) 1988-06-17 1988-06-17

Country Status (1)

Country Link
JP (1) JPH021927U (en)

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