JPS6150329U

JPS6150329U -

Info

Publication number: JPS6150329U
Application number: JP13544484U
Authority: JP
Priority date: 1984-09-06
Filing date: 1984-09-06
Publication date: 1986-04-04

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例たるデイレイライン
集積回路の等価回路図、第２図は従来のデイレイ
ライン集積回路の等価回路図である。１１…入力ゲート（第１のゲート）、１５…出
力ゲート（第２のゲート）、１６…出力ゲート（
第３のゲート）、１７，１９，２０…独立ゲート
。 FIG. 1 is an equivalent circuit diagram of a delay line integrated circuit according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a conventional delay line integrated circuit. 11...Input gate (first gate), 15...Output gate (second gate), 16...Output gate (
3rd gate), 17, 19, 20...independent gates.

Claims

[Scope of utility model registration request]

a coil group consisting of a plurality of coils connected in series; a capacitor group consisting of a plurality of capacitors having one end commonly connected and the other end connected to the coil;
The first, second, and third gates are connected to one end and the other end of the coil group and the series connection point, respectively, and the input end and output end thereof are isolated from and independent of the coil group and the capacitor group. 1. A delay line integrated circuit comprising: one or more independent gates connectable to the outside;