JPS645538U - - Google Patents

Info

Publication number
JPS645538U
JPS645538U JP9984687U JP9984687U JPS645538U JP S645538 U JPS645538 U JP S645538U JP 9984687 U JP9984687 U JP 9984687U JP 9984687 U JP9984687 U JP 9984687U JP S645538 U JPS645538 U JP S645538U
Authority
JP
Japan
Prior art keywords
band
terminal
tuning
coil
capacitor connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9984687U
Other languages
Japanese (ja)
Other versions
JPH046274Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9984687U priority Critical patent/JPH046274Y2/ja
Publication of JPS645538U publication Critical patent/JPS645538U/ja
Application granted granted Critical
Publication of JPH046274Y2 publication Critical patent/JPH046274Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Noise Elimination (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案回路の一実施例の回路図、第2
図は従来回路の一例の回路図、第3図は従来回路
のLW受信時の等価回路図である。 C〜C,CA,CB,CT…コンデンサ、
,L…同調コイル、Q〜Q…トランジ
スタ、R〜R,RD…抵抗。
Figure 1 is a circuit diagram of an embodiment of the circuit of the present invention, Figure 2 is a circuit diagram of an embodiment of the circuit of the present invention;
The figure is a circuit diagram of an example of a conventional circuit, and FIG. 3 is an equivalent circuit diagram of the conventional circuit when receiving LW. C1 to C4 , CA, CB, CT...capacitor,
L1 , L3 ...tuning coil, Q1 - Q4 ...transistor, R1 - R3 , RD...resistance.

Claims (1)

【実用新案登録請求の範囲】 受信信号の入力端子と同調した信号の出力端子
との間に直列接続された第1の帯域用の第1の同
調コイル及び第2の帯域用の第2の同調コイルと
、 該入力端子と共通端子との間を接続する第1の
コンデンサと、 第1の帯域受信時にのみ該第1及び第2の同調
コイルの接続点と共通端子との間を接続する第2
のコンデンサと、 第2の帯域受信時にのみ該出力端子と共通端子
との間を接続する第3のコンデンサとよりなるチ
ユーナの同調回路において、 第1の帯域受信時にのみ該第2の同調コイルの
両端間に接続する第4のコンデンサを設けてなる
チユーナの同調回路。
[Claims for Utility Model Registration] A first tuning coil for a first band and a second tuning coil for a second band connected in series between an input terminal for a received signal and an output terminal for a tuned signal. a first capacitor connected between the coil, the input terminal and the common terminal, and a first capacitor connected between the connection point of the first and second tuning coils and the common terminal only when receiving the first band. 2
and a third capacitor that connects the output terminal and the common terminal only when receiving the second band. A tuner tuning circuit including a fourth capacitor connected between both ends.
JP9984687U 1987-06-29 1987-06-29 Expired JPH046274Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9984687U JPH046274Y2 (en) 1987-06-29 1987-06-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9984687U JPH046274Y2 (en) 1987-06-29 1987-06-29

Publications (2)

Publication Number Publication Date
JPS645538U true JPS645538U (en) 1989-01-12
JPH046274Y2 JPH046274Y2 (en) 1992-02-20

Family

ID=31327384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9984687U Expired JPH046274Y2 (en) 1987-06-29 1987-06-29

Country Status (1)

Country Link
JP (1) JPH046274Y2 (en)

Also Published As

Publication number Publication date
JPH046274Y2 (en) 1992-02-20

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