JPH0277926U - - Google Patents

Info

Publication number
JPH0277926U
JPH0277926U JP15578988U JP15578988U JPH0277926U JP H0277926 U JPH0277926 U JP H0277926U JP 15578988 U JP15578988 U JP 15578988U JP 15578988 U JP15578988 U JP 15578988U JP H0277926 U JPH0277926 U JP H0277926U
Authority
JP
Japan
Prior art keywords
coil
tuner
pin diode
tuning circuit
signal level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15578988U
Other languages
Japanese (ja)
Other versions
JPH0441625Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15578988U priority Critical patent/JPH0441625Y2/ja
Publication of JPH0277926U publication Critical patent/JPH0277926U/ja
Application granted granted Critical
Publication of JPH0441625Y2 publication Critical patent/JPH0441625Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の回路図、第2図は
第1図に示す回路の同調特性の概略を示す図、第
3図は従来回路の回路図、第4図は第3図に示す
回路の同調特性の概略を示す図である。 1,3,4,5,6…入力端子、2…MOSF
ET、D〜D…pinダイオード、BD
BD…バラクタダイオード、L〜L…コイ
ル、R〜R…抵抗、C〜C…コンデンサ
、Q…トランジスタ。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram schematically showing the tuning characteristics of the circuit shown in Fig. 1, Fig. 3 is a circuit diagram of a conventional circuit, and Fig. 4 is a diagram showing the outline of the tuning characteristics of the circuit shown in Fig. 1. FIG. 2 is a diagram schematically showing the tuning characteristics of the circuit shown in FIG. 1, 3, 4, 5, 6...Input terminal, 2...MOSF
ET, D1 to D4 ...pin diode, BD1 ,
BD2 ...Varactor diode, L1 - L4 ...Coil, R1 - R5 ...Resistor, C1 - C3 ...Capacitor, Q...Transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 並列に接続されたコイルとコンデンサのうちい
ずれか一方または両方を可変することにより所定
周波数の信号を選択するFMチユーナの同調回路
において、該コイルを互いに誘導結合された1次
コイル及び2次コイルとし、該1次コイルに直列
にpinダイオを接続し、検出した信号レベルに
応じて該PINダイオードに加えるバイアス電圧
を変化させる信号レベル検出手段を具備してなる
FMチユーナの同調回路。
In an FM tuner tuning circuit that selects a signal of a predetermined frequency by varying one or both of a coil and a capacitor connected in parallel, the coils are used as a primary coil and a secondary coil that are inductively coupled to each other. A tuning circuit for an FM tuner, comprising: a pin diode connected in series to the primary coil; and signal level detection means for changing a bias voltage applied to the pin diode according to a detected signal level.
JP15578988U 1988-11-30 1988-11-30 Expired JPH0441625Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15578988U JPH0441625Y2 (en) 1988-11-30 1988-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15578988U JPH0441625Y2 (en) 1988-11-30 1988-11-30

Publications (2)

Publication Number Publication Date
JPH0277926U true JPH0277926U (en) 1990-06-14
JPH0441625Y2 JPH0441625Y2 (en) 1992-09-30

Family

ID=31433728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15578988U Expired JPH0441625Y2 (en) 1988-11-30 1988-11-30

Country Status (1)

Country Link
JP (1) JPH0441625Y2 (en)

Also Published As

Publication number Publication date
JPH0441625Y2 (en) 1992-09-30

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