JPS6433234U

JPS6433234U -

Info

Publication number: JPS6433234U
Application number: JP12938687U
Authority: JP
Priority date: 1987-08-25
Filing date: 1987-08-25
Publication date: 1989-03-01

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例としてのミキサ回路
を具備したテレビジヨンチユーナの構成を示すブ
ロツク図、第２図は前記ミキサ回路の回路図、第
３図ａ及びｂはそれぞれ本考案の実施例のミキサ
回路の利得特性を示したグラフである。第４図は
本考案の一実施例としてのミキサ回路を具備した
テレビジヨンチユーナの構成を示すブロツク図、
第５図は従来例のミキサ回路の回路図である。１……テレビジヨンチユーナ、２……ミキサ回
路、３……バイポーラトランジスタ、４，５……
コンデンサ、６……スイツチングダイオード、８
……ピーキングコイル。 FIG. 1 is a block diagram showing the configuration of a television tuner equipped with a mixer circuit as an embodiment of the present invention, FIG. 2 is a circuit diagram of the mixer circuit, and FIGS. 7 is a graph showing the gain characteristics of the mixer circuit of the example. FIG. 4 is a block diagram showing the configuration of a television tuner equipped with a mixer circuit as an embodiment of the present invention;
FIG. 5 is a circuit diagram of a conventional mixer circuit. 1... Television channel, 2... Mixer circuit, 3... Bipolar transistor, 4, 5...
Capacitor, 6...Switching diode, 8
...Peaking coil.

Claims

[Scope of utility model registration request]

The RF signal of the inter-stage tuned circuit is transmitted to a mixer circuit of bipolar elements via a peaking circuit, and the peaking circuit includes a first comprising a second capacitor and a peaking coil interposed between the connection of these capacitors and ground,
One of the first and second capacitors has a capacitance of 1.
A mixer circuit characterized in that the mixer circuit is set to a predetermined value within the range of 0 to 50 pF and which provides capacitive coupling when connected in series.