JPS6251825U - - Google Patents
Info
- Publication number
- JPS6251825U JPS6251825U JP14202085U JP14202085U JPS6251825U JP S6251825 U JPS6251825 U JP S6251825U JP 14202085 U JP14202085 U JP 14202085U JP 14202085 U JP14202085 U JP 14202085U JP S6251825 U JPS6251825 U JP S6251825U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- gate
- pulse generation
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Thyristor Switches And Gates (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は本考案例によるゲート回路の実施例のタイム
チヤート、第３図は制御回路と本考案例によるゲ
ート回路との接続の例を示す図、第４図は本考案
例の他の実施例のタイムチヤートを示す図、第５
図、第６図は従来例およびそのタイムチヤートを
示す図、第７図、第８図は他の従来例およびその
タイムチヤートを示す図である。
１…ＧＴＯ、２…ゲート回路、３…遅延回路、
４…単発パルス発生回路。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a time chart of an embodiment of the gate circuit according to the present invention, FIG. 3 is a diagram showing an example of the connection between the control circuit and the gate circuit according to the present invention, and FIG. 4 is a diagram showing another embodiment of the present invention. Diagram showing time chart, No. 5
6 are diagrams showing a conventional example and its time chart, and FIGS. 7 and 8 are diagrams showing another conventional example and its time chart. 1...GTO, 2...gate circuit, 3...delay circuit,
4...Single pulse generation circuit.
Claims (1)
、単発パルス発生回路の出力信号によつて付勢さ
れるオフゲート回路と、前記単発パルス発生回路
を付勢するナアンド回路と、該ナアンド回路の一
方の入力端子にゲートブロツク信号が印加され、
他方の入力端子に前記オン信号を遅延回路及びノ
ツト回路を各して印加するようにしたＧＴＯのゲ
ート回路。 an on-gate circuit energized by the on-signal; an off-gate circuit energized by the output signal of the single-shot pulse generation circuit; a NAND circuit that energizes the single-shot pulse generation circuit; and one of the NAND circuits. A gate block signal is applied to the input terminal,
A GTO gate circuit in which the on signal is applied to the other input terminal of a delay circuit and a not circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14202085U JPS6251825U (en) | 1985-09-19 | 1985-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14202085U JPS6251825U (en) | 1985-09-19 | 1985-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6251825U true JPS6251825U (en) | 1987-03-31 |
Family
ID=31050350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14202085U Pending JPS6251825U (en) | 1985-09-19 | 1985-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6251825U (en) |
-
1985
- 1985-09-19 JP JP14202085U patent/JPS6251825U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6251825U (en) | ||
| JPS6223349U (en) | ||
| JPH0293837U (en) | ||
| JPS61134125U (en) | ||
| JPS5883830U (en) | Trigger pulse generation circuit | |
| JPS60172434U (en) | Malfunction prevention circuit at startup | |
| JPS621430U (en) | ||
| JPS6183338U (en) | ||
| JPS62177128U (en) | ||
| JPS6130102U (en) | Control equipment for water heaters, etc. | |
| JPS5929843U (en) | electronic switch control circuit | |
| JPS63121918U (en) | ||
| JPS6316713U (en) | ||
| JPS61176825U (en) | ||
| JPS58522U (en) | Pulse width shaping circuit | |
| JPS6172933U (en) | ||
| JPS61121014U (en) | ||
| JPS6412488U (en) | ||
| JPS62159027U (en) | ||
| JPS5866878U (en) | Gate control circuit of gate turn-off thyristor | |
| JPS5899939U (en) | semiconductor logic circuit | |
| JPS60164242U (en) | key scan circuit | |
| JPS5882041U (en) | Reset signal generation circuit | |
| JPS6085490U (en) | remote control device | |
| JPS60114434U (en) | Pulse generation circuit |