JPS63198225U - - Google Patents

Info

Publication number
JPS63198225U
JPS63198225U JP8982587U JP8982587U JPS63198225U JP S63198225 U JPS63198225 U JP S63198225U JP 8982587 U JP8982587 U JP 8982587U JP 8982587 U JP8982587 U JP 8982587U JP S63198225 U JPS63198225 U JP S63198225U
Authority
JP
Japan
Prior art keywords
terminal
switching element
semiconductor switching
output terminal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8982587U
Other languages
Japanese (ja)
Other versions
JP2517538Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8982587U priority Critical patent/JP2517538Y2/en
Priority to US07/205,244 priority patent/US4872441A/en
Publication of JPS63198225U publication Critical patent/JPS63198225U/ja
Application granted granted Critical
Publication of JP2517538Y2 publication Critical patent/JP2517538Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による双安定回路
の回路図、第2図は他の実施例による双安定回路
の回路図、第3図は従来の双安定回路の回路図で
ある。 7……トランジスタ、9……NAND回路、1
1……NOR回路、a……入力端子、b……出力
端子、c……制御端子。なお、図中、同一符号は
同一または相当部分を示す。
FIG. 1 is a circuit diagram of a bistable circuit according to one embodiment of this invention, FIG. 2 is a circuit diagram of a bistable circuit according to another embodiment, and FIG. 3 is a circuit diagram of a conventional bistable circuit. 7...Transistor, 9...NAND circuit, 1
1...NOR circuit, a...input terminal, b...output terminal, c...control terminal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御極が入力端子に接続され、電源間に入力端
と出力端が接続された半導体スイツチング素子と
、第1入力端を制御端子とし、第2入力端を電源
と前記半導体スイツチング素子の入力端または出
力端との間に接続し、出力端を前記半導体スイツ
チング素子の制御極に接続すると共に出力端子に
接続してなる論理回路とを備えたことを特徴とす
る双安定回路。
a semiconductor switching element with a control pole connected to an input terminal, an input end and an output end connected between a power supply; a first input terminal as a control terminal; 1. A bistable circuit comprising: a logic circuit connected between the semiconductor switching element and the output terminal, the output terminal being connected to the control pole of the semiconductor switching element and the output terminal.
JP8982587U 1987-06-10 1987-06-10 Bistable circuit Expired - Lifetime JP2517538Y2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8982587U JP2517538Y2 (en) 1987-06-10 1987-06-10 Bistable circuit
US07/205,244 US4872441A (en) 1987-06-10 1988-06-10 Ignition circuit for internal combustion engine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8982587U JP2517538Y2 (en) 1987-06-10 1987-06-10 Bistable circuit

Publications (2)

Publication Number Publication Date
JPS63198225U true JPS63198225U (en) 1988-12-20
JP2517538Y2 JP2517538Y2 (en) 1996-11-20

Family

ID=30949155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8982587U Expired - Lifetime JP2517538Y2 (en) 1987-06-10 1987-06-10 Bistable circuit

Country Status (1)

Country Link
JP (1) JP2517538Y2 (en)

Also Published As

Publication number Publication date
JP2517538Y2 (en) 1996-11-20

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