JPS62186532U - - Google Patents
Info
- Publication number
- JPS62186532U JPS62186532U JP7504486U JP7504486U JPS62186532U JP S62186532 U JPS62186532 U JP S62186532U JP 7504486 U JP7504486 U JP 7504486U JP 7504486 U JP7504486 U JP 7504486U JP S62186532 U JPS62186532 U JP S62186532U
- Authority
- JP
- Japan
- Prior art keywords
- logic level
- input
- terminal
- output
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案のインバータ回路の一実施例の
回路図、第２図は従来のＴＴＬインバータ回路の
実施例の回路図、第３図は第２図のＴＴＬインバ
ータ回路の出力部を示す回路図である。
１……ＴＴＬインバータ回路、２，３……バイ
アス抵抗、４……トランジスタ、５，６……抵抗
、７……外部負荷抵抗、８……入力端子、９……
出力端子、１０……負荷抵抗、１１……トランジ
スタ、１２……ダイオード、１３……トランジス
タ、１４……電流、１６……端子。
Fig. 1 is a circuit diagram of an embodiment of the inverter circuit of the present invention, Fig. 2 is a circuit diagram of an embodiment of a conventional TTL inverter circuit, and Fig. 3 is a circuit diagram showing the output section of the TTL inverter circuit of Fig. 2. It is a diagram. 1... TTL inverter circuit, 2, 3... Bias resistor, 4... Transistor, 5, 6... Resistor, 7... External load resistance, 8... Input terminal, 9...
Output terminal, 10...Load resistance, 11...Transistor, 12...Diode, 13...Transistor, 14...Current, 16...Terminal.
Claims (1)
力端子から論理レベル“Ｌ”を出力するＴＴＬ論
理インバータ回路と、前記入力端子に論理レベル
“Ｌ”を入力したときスイツチング作動し論理レ
ベル“Ｈ”となる電源電圧を前記出力端子に供給
するスイツチング素子とを設けたことを特徴とす
るインバータ回路。 A TTL logic inverter circuit outputs a logic level "L" from an output terminal when a logic level "H" is input to the input terminal, and a switching operation is performed to output a logic level "H" when a logic level "L" is input to the input terminal. and a switching element for supplying a power supply voltage to the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7504486U JPS62186532U (en) | 1986-05-19 | 1986-05-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7504486U JPS62186532U (en) | 1986-05-19 | 1986-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62186532U true JPS62186532U (en) | 1987-11-27 |
Family
ID=30920827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7504486U Pending JPS62186532U (en) | 1986-05-19 | 1986-05-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62186532U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5367341A (en) * | 1976-11-27 | 1978-06-15 | Mitsubishi Electric Corp | Output circuit |
-
1986
- 1986-05-19 JP JP7504486U patent/JPS62186532U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5367341A (en) * | 1976-11-27 | 1978-06-15 | Mitsubishi Electric Corp | Output circuit |