JPS6399424U

JPS6399424U -

Info

Publication number: JPS6399424U
Application number: JP19554786U
Authority: JP
Priority date: 1986-12-19
Filing date: 1986-12-19
Publication date: 1988-06-28

Description

[Brief explanation of the drawing]

第１図はこの考案の第１の実施例によるＭＯＳ
ＦＥＴ駆動回路の回路図、第２図はこの考案の
第２の実施例によるＭＯＳＦＥＴ駆動回路の回
路図、第３図は第２図における信号ＳＡ，ＳＢの
波形図、第４図は従来のＭＯＳＦＥＴ駆動回路
の回路図、第５図は第４図のパルストランス３の
駆動パルスの波形図である。１，２，９，１０，１９，２０……トランジス
タ、３，１２，２２……パルストランス、８，１
１，２１……コンデンサ、７，１６，１８……Ｆ
ＥＴ、Ｓ５，Ｓ８，Ｓ１１……信号。 Figure 1 shows a MOS according to the first embodiment of this invention.
FIG. 2 is a circuit diagram of a MOS FET drive circuit according to a second embodiment of this invention, FIG. 3 is a waveform diagram of signals SA and SB in FIG. 2, and FIG. 4 is a diagram of a conventional MOS FET drive circuit. A circuit diagram of the MOS FET drive circuit, FIG. 5 is a waveform diagram of the drive pulse of the pulse transformer 3 of FIG. 4. 1, 2, 9, 10, 19, 20...transistor, 3, 12, 22...pulse transformer, 8, 1
1, 21...Capacitor, 7, 16, 18...F
ET, S5, S8, S11...signal.

Claims

[Scope of utility model registration request]

a switching element, a pulse transformer driven by the output of the switching element, and a MOS driven based on the output of the pulse transformer.
A MOS FET drive circuit comprising a FET, wherein a capacitor is inserted between the output terminal of the switching element and the input terminal of the pulse transformer.