JPS6433669U - - Google Patents
Info
- Publication number
- JPS6433669U JPS6433669U JP12526687U JP12526687U JPS6433669U JP S6433669 U JPS6433669 U JP S6433669U JP 12526687 U JP12526687 U JP 12526687U JP 12526687 U JP12526687 U JP 12526687U JP S6433669 U JPS6433669 U JP S6433669U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- mosfet
- gate
- series
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
第1図は本考案の実施例を示す回路図、第2図
は第1図に示された回路の動作を示す波形図、第
3図及び第4図は従来例を示す回路図である。
6……入力端子、7……第1の抵抗、10……
第2の抵抗、11……第3の抵抗、8……第1の
MOSFET、9……第2のMOSFET、12
……第3のMOSFET。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the circuit shown in FIG. 1, and FIGS. 3 and 4 are circuit diagrams showing a conventional example. 6...Input terminal, 7...First resistor, 10...
Second resistor, 11... Third resistor, 8... First MOSFET, 9... Second MOSFET, 12
...Third MOSFET.
Claims (1)
に直列接続された第1の抵抗、第1のMOSFE
T、及び、1以上の第2のMOSFETと、前記
端子と接地電位間に直列接続された第2の抵抗、
第3の抵抗及び第3のMOSFETとを備え、前
記第2の抵抗と第3の抵抗の接続点が前記第1の
MOSFETのゲートに接続され、前記第1の抵
抗と第1のMOSFETの接続点が前記第3のM
OSFETのゲートに接続されたことを特徴とす
る電圧検出回路。 a first resistor and a first MOSFE connected in series between a terminal to which a voltage to be detected is applied and ground potential;
T, one or more second MOSFETs, and a second resistor connected in series between the terminal and ground potential;
a third resistor and a third MOSFET, a connection point between the second resistor and the third resistor is connected to a gate of the first MOSFET, and a connection point between the first resistor and the first MOSFET; The point is the third M
A voltage detection circuit characterized in that it is connected to the gate of an OSFET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12526687U JPH0537251Y2 (en) | 1987-08-18 | 1987-08-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12526687U JPH0537251Y2 (en) | 1987-08-18 | 1987-08-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6433669U true JPS6433669U (en) | 1989-03-02 |
JPH0537251Y2 JPH0537251Y2 (en) | 1993-09-21 |
Family
ID=31375720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12526687U Expired - Lifetime JPH0537251Y2 (en) | 1987-08-18 | 1987-08-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0537251Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04166330A (en) * | 1990-10-30 | 1992-06-12 | Toray Ind Inc | Easily fusable heat-insulation fiber mat and its manufacture |
-
1987
- 1987-08-18 JP JP12526687U patent/JPH0537251Y2/ja not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04166330A (en) * | 1990-10-30 | 1992-06-12 | Toray Ind Inc | Easily fusable heat-insulation fiber mat and its manufacture |
Also Published As
Publication number | Publication date |
---|---|
JPH0537251Y2 (en) | 1993-09-21 |
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