JPS6126326U

JPS6126326U - Initial state setting device

Info

Publication number: JPS6126326U
Application number: JP11062284U
Authority: JP
Inventors: 賢一村脇; 裕二北村
Original assignee: 三洋電機株式会社
Priority date: 1984-07-20
Filing date: 1984-07-20
Publication date: 1986-02-17
Anticipated expiration: 1999-07-20
Also published as: JPH0731626Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案装置の１実施例の回路構成図、第２図は
第１図中の同符号の波形説明図、第３図、第４区は本考
案装置のそれそれ他の実施例の回路構成図、第５図、第
６図は本考案装置の更に他の実施例の回路構成図と波形
説明図、第７図は従来装置の回路構成図、第８図は第７
図中の各部の波形図、第９図、第１０図は他の従来装置
の回路構成図、第１１図は初期状態設定信号の利用され
るフリツプフロツブ回路の回路図である。主な符号の説明、２・・・第１抵抗、３・・・ダイオー
ド、４，６・・・第１、第２のＭＯＳＦＥＴ，１１・
・・ＣＭＯＳ回路、８・・・遅延回路。Fig. 1 is a circuit configuration diagram of one embodiment of the device of the present invention, Fig. 2 is an explanatory diagram of waveforms with the same symbols in Fig. 1, and Figs. 3 and 4 are other embodiments of the device of the present invention. 5 and 6 are circuit diagrams and waveform explanatory diagrams of still other embodiments of the device of the present invention, FIG. 7 is a circuit diagram of the conventional device, and FIG.
9 and 10 are circuit configuration diagrams of other conventional devices, and FIG. 11 is a circuit diagram of a flip-flop circuit in which an initial state setting signal is used. Explanation of main symbols, 2... First resistor, 3... Diode, 4, 6... First and second MOSFET, 1 1.
...CMOS circuit, 8...delay circuit.

Claims

[Scope of utility model registration request]

(1) In the initial state setting device that sets the device to a certain state when the power is turned on, the gate and drain are connected from the power supply voltage Voo through the first resistor and the diode connected in the forward direction, and the source is grounded. The first MOSFE
T, a second MOSFET whose gate is connected to a connection point between the first resistor and the diode, whose drain is grounded via a second resistor, and whose source is connected to the power supply voltage VDD; a CMOS circuit including an input circuit to which an output signal is connected;
The sum of the threshold voltage of the ET and the second MOSFET and the forward voltage of the diode is compared with the power supply voltage VDD, and the output of the CMOS circuit is set as an initial state setting signal. Characteristic initial state setting device.

(2) The output signal of the second MOSFET is
The initial state setting device according to claim 1, which is applied to the input circuit of the CMOS circuit via a delay circuit including a third resistor to which the drain of an OSFET is connected. .

(3) The first, second, and third resistors are each MO for resistance.
The initial state setting device according to claim (2) of the utility model registration, characterized in that it is constituted by an SFET.