JPS599638U - Simple D/A converter - Google Patents
Simple D/A converterInfo
- Publication number
- JPS599638U JPS599638U JP10346782U JP10346782U JPS599638U JP S599638 U JPS599638 U JP S599638U JP 10346782 U JP10346782 U JP 10346782U JP 10346782 U JP10346782 U JP 10346782U JP S599638 U JPS599638 U JP S599638U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- converter
- resistors
- output stages
- constant voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案による簡易形Ｄ／Ａ便換器の１つの実
施例としての回路図、第２図は、本考案の原理を示す電
圧加算回路図、第３図は、本考案の他の実施例を示す回
路図、第４図は第３図に示す回路の時間的動作を示す説
明図であり、入力ディジタル信号（パルス列）と対応す
るアナログ出力波形を示している。
２１〜２Ｎ・・・ＣＭＬゲート（バッファ）、３１〜３
Ｎ・・・第１の抵抗器、４・・・第２の抵抗器、５・・
・−アナログ出力端子、６・・・電源端子、２０１〜２
ＯＮ・・・定電圧電源、３１〜３Ｎ・・・第１抵抗器、
４・・・第２の抵抗器、５・・・アナログ出力端子、６
０・・・定電圧電源、１０１・・・クロックパルス入力
端子、１０２・・・リセットパルス入力端子、１０３・
・・ラッチパルス入力端子、２・・・ラッチ、２０・・
・シフトレジスタ、３・・・集積化抵抗器、３１〜３４
・・・第１の抵抗器、４・・・第２の抵抗器、５・・・
アナログ出力端子。Fig. 1 is a circuit diagram of one embodiment of a simple D/A toilet exchanger according to the present invention, Fig. 2 is a voltage addition circuit diagram showing the principle of the present invention, and Fig. 3 is a circuit diagram of a simple D/A toilet exchanger according to the present invention. FIG. 4, a circuit diagram showing another embodiment, is an explanatory diagram showing the temporal operation of the circuit shown in FIG. 3, and shows an analog output waveform corresponding to an input digital signal (pulse train). 21~2N...CML gate (buffer), 31~3
N...first resistor, 4...second resistor, 5...
-Analog output terminal, 6...power supply terminal, 201-2
ON...constant voltage power supply, 31~3N...first resistor,
4... Second resistor, 5... Analog output terminal, 6
0... Constant voltage power supply, 101... Clock pulse input terminal, 102... Reset pulse input terminal, 103...
...Latch pulse input terminal, 2...Latch, 20...
・Shift register, 3... integrated resistor, 31 to 34
...first resistor, 4...second resistor, 5...
Analog output terminal.
Claims (1)
ぞれ接続された抵抗値が等しいＮ個の第１の抵抗器と、
一端が前記Ｎ個の第１の抵抗器に共通に接続され、他端
が定電圧定源に接続される１個の第２の抵抗器とから構
成したことを特徴とする簡易形Ｄ／Ａ変換器。N arbitrary CML output stages, N first resistors with equal resistance values connected to each stage of the output stages,
A simplified D/A comprising: one second resistor, one end of which is commonly connected to the N first resistors, and the other end of which is connected to a constant voltage constant source. converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10346782U JPS599638U (en) | 1982-07-08 | 1982-07-08 | Simple D/A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10346782U JPS599638U (en) | 1982-07-08 | 1982-07-08 | Simple D/A converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS599638U true JPS599638U (en) | 1984-01-21 |
Family
ID=30243397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10346782U Pending JPS599638U (en) | 1982-07-08 | 1982-07-08 | Simple D/A converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599638U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012514406A (en) * | 2008-12-30 | 2012-06-21 | エスティー‐エリクソン、ソシエテ、アノニム | Digital to analog converter |
-
1982
- 1982-07-08 JP JP10346782U patent/JPS599638U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012514406A (en) * | 2008-12-30 | 2012-06-21 | エスティー‐エリクソン、ソシエテ、アノニム | Digital to analog converter |
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