JPS5933336U - Simple digital to analog converter - Google Patents
Simple digital to analog converterInfo
- Publication number
- JPS5933336U JPS5933336U JP12796582U JP12796582U JPS5933336U JP S5933336 U JPS5933336 U JP S5933336U JP 12796582 U JP12796582 U JP 12796582U JP 12796582 U JP12796582 U JP 12796582U JP S5933336 U JPS5933336 U JP S5933336U
- Authority
- JP
- Japan
- Prior art keywords
- analog converter
- simple digital
- resistor
- output
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の第１の実施例を示す回路図、第２図は
本考案の第２の実施例を示す回路図、第３図は上記第２
の実施例の入力デジタル信号と出力アナログ信号との関
係を示すタイムチャートである。
図において、２・・・デコーダ、４・・・第２の抵抗器
、５・・・アナログ出力端子、６・・・電源端子、１１
〜１Ｎ・・・入力端子、２１〜２Ｎ・・・バッファ、３
１〜３Ｎ・・・第１の抵抗器、１０１〜１０３・・・入
力端子。Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the present invention, and Fig. 3 is a circuit diagram showing a second embodiment of the invention.
3 is a time chart showing the relationship between the input digital signal and the output analog signal of the embodiment. In the figure, 2... Decoder, 4... Second resistor, 5... Analog output terminal, 6... Power supply terminal, 11
~1N...Input terminal, 21~2N...Buffer, 3
1 to 3N...first resistor, 101 to 103...input terminal.
Claims (1)
か１個のみが低インピーダンスとなるデコーダと、該デ
コーダの複数の出力端子にそれぞれ一端が接続された複
数の第１抵抗器と、一端を前記複数の第１の抵抗器の他
端に共通に接続し他端を電源に接続した第２の抵抗器と
を備えて、前記デコーダに入力されたデジタル信号に対
応したアナログ信号を前記第２の抵抗器と前記第１の抵
抗器との接続点から出力することを特徴とする簡易形デ
ジタル・アナログ変換器。a decoder in which only one of the plurality of output terminals has a low impedance according to an input digital signal; a plurality of first resistors each having one end connected to the plurality of output terminals of the decoder; a second resistor connected in common to the other ends of the plurality of first resistors and the other end connected to a power supply; A simple digital-to-analog converter, characterized in that an output is output from a connection point between a resistor and the first resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12796582U JPS5933336U (en) | 1982-08-26 | 1982-08-26 | Simple digital to analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12796582U JPS5933336U (en) | 1982-08-26 | 1982-08-26 | Simple digital to analog converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5933336U true JPS5933336U (en) | 1984-03-01 |
Family
ID=30290453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12796582U Pending JPS5933336U (en) | 1982-08-26 | 1982-08-26 | Simple digital to analog converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933336U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55133128A (en) * | 1979-04-04 | 1980-10-16 | Nec Corp | D/a converter |
| JPS5721126A (en) * | 1980-07-15 | 1982-02-03 | Matsushita Electric Works Ltd | Analog conversion circuit for digital signal |
-
1982
- 1982-08-26 JP JP12796582U patent/JPS5933336U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55133128A (en) * | 1979-04-04 | 1980-10-16 | Nec Corp | D/a converter |
| JPS5721126A (en) * | 1980-07-15 | 1982-02-03 | Matsushita Electric Works Ltd | Analog conversion circuit for digital signal |
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