JPS58141611U - Digital-to-analog converter output buffer circuit - Google Patents
Digital-to-analog converter output buffer circuitInfo
- Publication number
- JPS58141611U JPS58141611U JP3892682U JP3892682U JPS58141611U JP S58141611 U JPS58141611 U JP S58141611U JP 3892682 U JP3892682 U JP 3892682U JP 3892682 U JP3892682 U JP 3892682U JP S58141611 U JPS58141611 U JP S58141611U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- analog converter
- output buffer
- buffer circuit
- converter output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図および第2図は従来の出力バッファ回路の構成例
を示す回路図、第3図はこの考案による出力バッファ回
路の基本構成を示す回路図、第4図はこの考案による出
力バッファ回路の具体回路の一例を示す回路図である。
1・・・・・・デジタルアナログ変換器、(D/Aコン
バータ)、7・・・・・・カレントミラー回路、8・・
・・・・負荷抵抗(抵抗)、9・・・・・・出力端子、
13.15・・・・・・PNPトランジスタ。1 and 2 are circuit diagrams showing an example of the configuration of a conventional output buffer circuit, FIG. 3 is a circuit diagram showing the basic configuration of an output buffer circuit according to this invention, and FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer circuit according to this invention. FIG. 2 is a circuit diagram showing an example of a specific circuit. 1...Digital analog converter, (D/A converter), 7...Current mirror circuit, 8...
...Load resistance (resistance), 9...Output terminal,
13.15...PNP transistor.
Claims (1)
グ変換器の出力電流が流れるように構成亨ると共に、こ
のカレントミラー回路の他方の電流経路に直列に介挿さ
れた負荷抵抗の両端間電圧を出力信号として取出すよう
に構成したことを特徴とするデジタルアナログ変換器の
出力バッファ回路。The current mirror circuit is configured so that the output current of the digital-to-analog converter flows through one current path, and the voltage across a load resistor inserted in series in the other current path of this current mirror circuit is output as a signal. 1. An output buffer circuit for a digital-to-analog converter, characterized in that the output buffer circuit is configured to take out the output as a digital-to-analog converter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3892682U JPS58141611U (en) | 1982-03-19 | 1982-03-19 | Digital-to-analog converter output buffer circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3892682U JPS58141611U (en) | 1982-03-19 | 1982-03-19 | Digital-to-analog converter output buffer circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58141611U true JPS58141611U (en) | 1983-09-24 |
Family
ID=30050236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3892682U Pending JPS58141611U (en) | 1982-03-19 | 1982-03-19 | Digital-to-analog converter output buffer circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58141611U (en) |
-
1982
- 1982-03-19 JP JP3892682U patent/JPS58141611U/en active Pending
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