JPS5934393U - Integrated circuit with test terminals - Google Patents
Integrated circuit with test terminalsInfo
- Publication number
- JPS5934393U JPS5934393U JP9458883U JP9458883U JPS5934393U JP S5934393 U JPS5934393 U JP S5934393U JP 9458883 U JP9458883 U JP 9458883U JP 9458883 U JP9458883 U JP 9458883U JP S5934393 U JPS5934393 U JP S5934393U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- integrated circuit
- gate
- test terminals
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electric Clocks (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示した電気回路図、第２図
は第１図の動作説明のためのタイムチャートである。
Ｄｌ・・・・・・第１の回路、Ｄ２・・・・・・第２の
回路、Ｆ工〜Ｆ５・・・・・・フリップフロップ回路、
Ｇ１〜Ｇ９・・・・・・ゲート回路、Ｖｌ、Ｖ２．■３
・・・・・・インバータ、Ｔ・・・・・・伝達ゲート、
Ｒ１，Ｒ２，Ｒ３・・・・・・抵抗、Ｓｌ、Ｓ２・・曲
スイッチ。FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1. Dl...first circuit, D2...second circuit, F~F5...flip-flop circuit,
G1 to G9...Gate circuit, Vl, V2. ■３
...Inverter, T...Transmission gate,
R1, R2, R3...Resistance, Sl, S2...Song switch.
Claims (1)
第１の回路の出力側に設けたゲート回路と、このゲート
回路の出力側に設けた第２の回路と、上記手動スイッチ
の操作に応答して選択的に上記ゲート回路の開閉および
第２の回路のリセットを行なう論理回路とを含む集積回
路からなり、少なくとも第２の回路の出力端子と第２の
回路の入力側から導出した端子とを集積回路の外部端子
とした検査端子を設けた集積回路。a first circuit having a manual switch and producing a pulse train;
A gate circuit provided on the output side of the first circuit, a second circuit provided on the output side of the gate circuit, and a gate circuit that selectively opens and closes the gate circuit and controls the second circuit in response to the operation of the manual switch. An integrated circuit comprising an integrated circuit including a logic circuit for resetting the circuit, and provided with a test terminal using at least an output terminal of a second circuit and a terminal derived from the input side of the second circuit as external terminals of the integrated circuit. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9458883U JPS5934393U (en) | 1983-06-20 | 1983-06-20 | Integrated circuit with test terminals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9458883U JPS5934393U (en) | 1983-06-20 | 1983-06-20 | Integrated circuit with test terminals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5934393U true JPS5934393U (en) | 1984-03-03 |
| JPS6123835Y2 JPS6123835Y2 (en) | 1986-07-16 |
Family
ID=30226347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9458883U Granted JPS5934393U (en) | 1983-06-20 | 1983-06-20 | Integrated circuit with test terminals |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5934393U (en) |
-
1983
- 1983-06-20 JP JP9458883U patent/JPS5934393U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6123835Y2 (en) | 1986-07-16 |
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