JPS6090934U

JPS6090934U - Jitter generation circuit

Info

Publication number: JPS6090934U
Application number: JP1983182145U
Authority: JP
Inventors: 牧野　哲男
Original assignee: 株式会社東芝
Priority date: 1983-11-28
Filing date: 1983-11-28
Publication date: 1985-06-21

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はセットアツプ時間とホールド時間を厳守しない
と正常動作を保障できない素子の一例を示した図、第２
図は第１図の素子の動作波形図、第３図は第１図の素子
が正常動作をしない場合の動作波形図、第４図は従来の
非同期発生回路の一例を示したブロック図、第５図は本
考案のジッダ発生回路の一実施例を示したブロック図、
第６図は第５図に示した回路の動作波形図、第７図は第
５図で示したジッダ発生回路の具体例を示したブロック
図、第８図は第７図に示した回路の動作波形図である。５１．５２，５３，５４・・・・・・オープンコレクタ
ＩＣ，５５，５６，５７，５８・・・・・・抵抗器、５
９・・・・・・コンデンサ、６０・・・・・・プルアッ
プ抵抗器、６１・・・・・・インバニタ。Figure 1 shows an example of an element whose normal operation cannot be guaranteed unless the set-up and hold times are strictly observed.
The figure is an operation waveform diagram of the element in Figure 1, Figure 3 is an operation waveform diagram when the element in Figure 1 does not operate normally, Figure 4 is a block diagram showing an example of a conventional asynchronous generating circuit, Figure 5 is a block diagram showing an embodiment of the jedder generation circuit of the present invention.
6 is an operating waveform diagram of the circuit shown in FIG. 5, FIG. 7 is a block diagram showing a specific example of the jitter generation circuit shown in FIG. 5, and FIG. 8 is a diagram of the circuit shown in FIG. 7. It is an operation waveform diagram. 51.52,53,54...Open collector IC, 55,56,57,58...Resistor, 5
9...Capacitor, 60...Pull-up resistor, 61...Invanitor.

Claims

[Scope of utility model registration request]

Multiple open collector ICs and each open collector I
The same number of resistors as the open 5 collector ICs are connected in series to the output side of C, a charging/discharging capacitor is connected to a common point with the other ends of these resistors, and one of the plurality of open collector ICs. a control circuit that applies a high or low level signal to each input of the plurality of open collector ICs, and a control circuit that applies a reference signal pulse to a point where the other inputs of the plurality of open collector ICs are commonly connected; A jitter generation circuit characterized in that a voltage is applied to a connection point between a charging and discharging capacitor and an output pulse is extracted from this connection point. −