JPH0370429U - - Google Patents
Info
- Publication number
- JPH0370429U JPH0370429U JP13116789U JP13116789U JPH0370429U JP H0370429 U JPH0370429 U JP H0370429U JP 13116789 U JP13116789 U JP 13116789U JP 13116789 U JP13116789 U JP 13116789U JP H0370429 U JPH0370429 U JP H0370429U
- Authority
- JP
- Japan
- Prior art keywords
- input
- mos transistor
- channel mos
- channel
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 claims 5
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案回路を示す回路図、第２図は第
１図の特性を示す特性図、第３図は従来回路を示
す回路図、第４図は第３図の特性を示す特性図で
ある。
１……入力端子、３……ＰチヤンネルＭＯＳト
ランジスタ、４……出力端子、５……Ｎチヤンネ
ルＭＯＳトランジスタ、６……ＮＡＮＤゲート、
７，９……インバータ、８……ＮＯＲゲート。
Fig. 1 is a circuit diagram showing the circuit of the present invention, Fig. 2 is a characteristic diagram showing the characteristics of Fig. 1, Fig. 3 is a circuit diagram showing the conventional circuit, and Fig. 4 is a characteristic diagram showing the characteristics of Fig. 3. It is. 1...Input terminal, 3...P channel MOS transistor, 4...Output terminal, 5...N channel MOS transistor, 6...NAND gate,
7, 9...Inverter, 8...NOR gate.
Claims (1)
たＰチヤンネルＭＯＳトランジスタと、前記出力
端子とアースとの間に出力路が接続されたＮチヤ
ンネルＭＯＳトランジスタとを備え、前記Ｐチヤ
ンネルＭＯＳトランジスタ及び前記Ｎチヤンネル
ＭＯＳトランジスタの入力に入力信号を反転入力
して前記出力端子から出力信号を得るバツフアに
おいて、 前記ＰチヤンネルＭＯＳトランジスタ及び前記
ＮチヤンネルＭＯＳトランジスタの出力路に貫通
電流が流れるのを防止する防止回路を、前記入力
信号が入力される入力端子と前記ＰチヤンネルＭ
ＯＳトランジスタ及び前記ＮチヤンネルＭＯＳト
ランジスタの入力との間に設けたことを特徴とす
るバツフアの貫通電流防止回路。 (2) 前記防止回路は、一方の入力が前記入力端
子と接続され、他方の入力が第１のインバータを
介して前記ＮチヤンネルＭＯＳトランジスタの入
力と接続され、出力が前記ＰチヤンネルＭＯＳト
ランジスタの入力と接続された論理積回路と、一
方の入力が前記入力端子と接続され、他方の入力
が第２のインバータを介して前記ＰチヤンネルＭ
ＯＳトランジスタの入力と接続され、出力が前記
ＮチヤンネルＭＯＳトランジスタの入力と接続さ
れた論理和回路と、より成ることを特徴とする請
求項(1)記載のバツフアの貫通電流防止回路。 (3) 前記第２のインバータのスレツシヨルドレ
ベルを前記第１のインバータのスレツシヨルドレ
ベルより大としたことを特徴とする請求項(2)記
載のバツフアの貫通電流防止回路。[Claims for Utility Model Registration] (1) A P-channel MOS transistor with an output path connected between a power source and an output terminal, and an N-channel MOS transistor with an output path connected between the output terminal and ground. an output path of the P-channel MOS transistor and the N-channel MOS transistor; A prevention circuit is provided between the input terminal to which the input signal is input and the P channel M.
A buffer through-current prevention circuit, characterized in that it is provided between an OS transistor and an input of the N-channel MOS transistor. (2) The prevention circuit has one input connected to the input terminal, the other input connected to the input of the N-channel MOS transistor via a first inverter, and the output connected to the input of the P-channel MOS transistor. an AND circuit connected to the P channel M, one input of which is connected to the input terminal, and the other input connected to the P channel M through a second inverter.
2. The buffer through-current prevention circuit according to claim 1, further comprising an OR circuit connected to an input of the OS transistor and having an output connected to the input of the N-channel MOS transistor. (3) The buffer through-current prevention circuit according to claim (2), wherein the threshold level of the second inverter is higher than the threshold level of the first inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13116789U JPH0370429U (en) | 1989-11-10 | 1989-11-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13116789U JPH0370429U (en) | 1989-11-10 | 1989-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0370429U true JPH0370429U (en) | 1991-07-15 |
Family
ID=31678690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13116789U Pending JPH0370429U (en) | 1989-11-10 | 1989-11-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0370429U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60165117A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Cmos output circuit |
| JPS62200821A (en) * | 1986-02-27 | 1987-09-04 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPS6432719A (en) * | 1987-07-29 | 1989-02-02 | Seiko Instr & Electronics | Output device for semiconductor integrated circuit |
| JPH02114718A (en) * | 1988-10-25 | 1990-04-26 | Nec Corp | Output buffer circuit |
-
1989
- 1989-11-10 JP JP13116789U patent/JPH0370429U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60165117A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Cmos output circuit |
| JPS62200821A (en) * | 1986-02-27 | 1987-09-04 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPS6432719A (en) * | 1987-07-29 | 1989-02-02 | Seiko Instr & Electronics | Output device for semiconductor integrated circuit |
| JPH02114718A (en) * | 1988-10-25 | 1990-04-26 | Nec Corp | Output buffer circuit |
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