JPS56140719A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS56140719A
JPS56140719A JP4301180A JP4301180A JPS56140719A JP S56140719 A JPS56140719 A JP S56140719A JP 4301180 A JP4301180 A JP 4301180A JP 4301180 A JP4301180 A JP 4301180A JP S56140719 A JPS56140719 A JP S56140719A
Authority
JP
Japan
Prior art keywords
inverter
betar
channel
mos transistor
amplification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4301180A
Other languages
Japanese (ja)
Inventor
Kanichi Miyazawa
Kazuhide Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4301180A priority Critical patent/JPS56140719A/en
Publication of JPS56140719A publication Critical patent/JPS56140719A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To set the bias point of an inverter at VDD/2 and at the same time increasing the degree of amplification, by setting the betaR (gm of driving side transistor/ gm of load side transistor) of a bias circuit equal to or larger than the betaR of the inverter. CONSTITUTION:The betaR of an inverter consisting of the depression MOS transistor 17 of N channel and the enhancement MOS transistor 18 of N channel is set larger than that of the ordinary logic circuit to increase the degree of amplification. A connection is given between the depression MOS transistor 13 of N channel and the enhancement MOS transistor 14 of N channel to form a bias circuit. Then the betaR of this bias circuit is set larger than that of an inverter. In this way, the bias point of the inverter can be set at VDD/2 without worsening the degree of amplification.
JP4301180A 1980-04-02 1980-04-02 Semiconductor circuit Pending JPS56140719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4301180A JPS56140719A (en) 1980-04-02 1980-04-02 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4301180A JPS56140719A (en) 1980-04-02 1980-04-02 Semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS56140719A true JPS56140719A (en) 1981-11-04

Family

ID=12652036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4301180A Pending JPS56140719A (en) 1980-04-02 1980-04-02 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS56140719A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184825A (en) * 1982-04-01 1983-10-28 ジ−メンス・アクチエンゲゼルシヤフト Electric signal amplifying device
JPS60105320A (en) * 1983-11-14 1985-06-10 Nippon Telegr & Teleph Corp <Ntt> Level converting circuit
JPWO2007116468A1 (en) * 2006-03-31 2009-08-20 富士通株式会社 Threshold correction circuit, circuit and circuit board with threshold correction function

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184825A (en) * 1982-04-01 1983-10-28 ジ−メンス・アクチエンゲゼルシヤフト Electric signal amplifying device
JPS60105320A (en) * 1983-11-14 1985-06-10 Nippon Telegr & Teleph Corp <Ntt> Level converting circuit
JPWO2007116468A1 (en) * 2006-03-31 2009-08-20 富士通株式会社 Threshold correction circuit, circuit and circuit board with threshold correction function
JP4638939B2 (en) * 2006-03-31 2011-02-23 富士通株式会社 Threshold correction circuit, circuit and circuit board with threshold correction function

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