JPS57199334A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS57199334A
JPS57199334A JP56083863A JP8386381A JPS57199334A JP S57199334 A JPS57199334 A JP S57199334A JP 56083863 A JP56083863 A JP 56083863A JP 8386381 A JP8386381 A JP 8386381A JP S57199334 A JPS57199334 A JP S57199334A
Authority
JP
Japan
Prior art keywords
mos
driving
constitution
input variable
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56083863A
Other languages
Japanese (ja)
Inventor
Tadaaki Masumori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56083863A priority Critical patent/JPS57199334A/en
Publication of JPS57199334A publication Critical patent/JPS57199334A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a circuit with less number of logical stages, by using an N-MOS transistor as a driving transistor(TR) in case of a P-MOS constitution and a P-MOS TR as the driving TR in case of a N-MOS constitution and realizing a logical function corresponding to NOT. CONSTITUTION:An N-MOS constitution consisting of P type semiconductor substrate 50 is taken as the base for the substrate, and a P-MOS transistor(TR) 52 in an N-well 51 provided on the substrate 50 is used for the inversion of an input variable. As a load element , N-channel depletion type TRT1 is used, and an N-channel enhancement type TRT2 for the affirmative input is used for a TR for an input variable A as a driving TR, and a P-channel depletion type TRT3 for negative input is used for a TR for an input variable B. Further a circuit output is picked up from a connecting point 53 between the load element TRT1 and the driving TRT2.
JP56083863A 1981-06-02 1981-06-02 Semiconductor integrated circuit Pending JPS57199334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56083863A JPS57199334A (en) 1981-06-02 1981-06-02 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56083863A JPS57199334A (en) 1981-06-02 1981-06-02 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57199334A true JPS57199334A (en) 1982-12-07

Family

ID=13814507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56083863A Pending JPS57199334A (en) 1981-06-02 1981-06-02 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57199334A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140725A (en) * 1983-01-31 1984-08-13 Nec Corp Logical circuit
US7679036B2 (en) 2004-03-18 2010-03-16 Roctool Method and device for inductively heating conductive elements in order to shape objects

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342456U (en) * 1976-09-16 1978-04-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342456U (en) * 1976-09-16 1978-04-12

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140725A (en) * 1983-01-31 1984-08-13 Nec Corp Logical circuit
US7679036B2 (en) 2004-03-18 2010-03-16 Roctool Method and device for inductively heating conductive elements in order to shape objects

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