JPS5767333A - Mos integrated circuit - Google Patents

Mos integrated circuit

Info

Publication number
JPS5767333A
JPS5767333A JP55144980A JP14498080A JPS5767333A JP S5767333 A JPS5767333 A JP S5767333A JP 55144980 A JP55144980 A JP 55144980A JP 14498080 A JP14498080 A JP 14498080A JP S5767333 A JPS5767333 A JP S5767333A
Authority
JP
Japan
Prior art keywords
level
voltage
integrated circuit
wide
mos integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55144980A
Other languages
Japanese (ja)
Inventor
Etsuo Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55144980A priority Critical patent/JPS5767333A/en
Publication of JPS5767333A publication Critical patent/JPS5767333A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET

Abstract

PURPOSE:To reduce power consumption and an are, which the MOS integrated circuit constituting a NAND circuit occupies on a chip, by varying the width of the input gate in this MOS integrated circuit. CONSTITUTION:A load capacity CO is provided in the output part of a two-input NAND circuit, and voltages V1 and V2 are applied to driving transistors TRs 1 and 2, and an output voltage V3 is applied to the gate of a TR0 for load. When the gate of the TR0 is 3mum long and 5mum wide and TRs 1 and 2 are 3mum long together and are 30mum wide and 60mum wide repsectively, the response characteristic of the voltage V3 has rapid rise and fall it the voltage V2 is changed from the H level to the L level at time t=0 or is changed from the L level to the H level at time t=20nsec while keeping the voltage V1 in the H level.
JP55144980A 1980-10-15 1980-10-15 Mos integrated circuit Pending JPS5767333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55144980A JPS5767333A (en) 1980-10-15 1980-10-15 Mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55144980A JPS5767333A (en) 1980-10-15 1980-10-15 Mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5767333A true JPS5767333A (en) 1982-04-23

Family

ID=15374671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55144980A Pending JPS5767333A (en) 1980-10-15 1980-10-15 Mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5767333A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884537A (en) * 1981-10-30 1983-05-20 ウエスターン・エレクトリック・カムパニー・インコーポレーテッド Insulated gate field effect transistor circuit
JPH01129612A (en) * 1987-11-16 1989-05-22 Matsushita Electric Ind Co Ltd Semiconductor circuit
JPH02117212A (en) * 1988-10-27 1990-05-01 Fujitsu Ltd Nand circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884537A (en) * 1981-10-30 1983-05-20 ウエスターン・エレクトリック・カムパニー・インコーポレーテッド Insulated gate field effect transistor circuit
JPH01129612A (en) * 1987-11-16 1989-05-22 Matsushita Electric Ind Co Ltd Semiconductor circuit
JP2553594B2 (en) * 1987-11-16 1996-11-13 松下電器産業株式会社 Semiconductor circuit
JPH02117212A (en) * 1988-10-27 1990-05-01 Fujitsu Ltd Nand circuit
EP0366489A2 (en) * 1988-10-27 1990-05-02 Fujitsu Limited Nand gate circuits
JP2555165B2 (en) * 1988-10-27 1996-11-20 富士通株式会社 NAND circuit

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