JPS55112037A - Static type mos circuit - Google Patents

Static type mos circuit

Info

Publication number
JPS55112037A
JPS55112037A JP1717979A JP1717979A JPS55112037A JP S55112037 A JPS55112037 A JP S55112037A JP 1717979 A JP1717979 A JP 1717979A JP 1717979 A JP1717979 A JP 1717979A JP S55112037 A JPS55112037 A JP S55112037A
Authority
JP
Japan
Prior art keywords
fetq3
high level
input signal
source
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1717979A
Other languages
Japanese (ja)
Inventor
Keizo Aoyama
Hiroshi Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1717979A priority Critical patent/JPS55112037A/en
Publication of JPS55112037A publication Critical patent/JPS55112037A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Abstract

PURPOSE:To obtain a static type MOS circuit which operates on the input signal of a small amplitude, by connecting the 2nd transistor receiving application of the input signal to the source of the 1st transistor receiving application of the power- down control signal. CONSTITUTION:Input signal IN to be applied to the gate of 2nd enhancement-type MOSFETQ3 is set to a high level while chip selection signal CS to be applied to the gate of 1st enhancement-type MOSFETQ2 is kept at a high level. Thus FETQ3 becomes conductive with output OUT turned to a low level. While in case signal IN is set to a low level, FETQ3 becomes nonconductive with OUT turned to a high level to secure the function as an inverter. At this moment, the source of FETQ3 is connected directly to power source VSS via no other element. Thus no voltage drop is caused between VSS and the source of FETQ3. And for the high level of the input signal, the allowable minimum threshold value of FETQ3 will do enough.
JP1717979A 1979-02-19 1979-02-19 Static type mos circuit Pending JPS55112037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1717979A JPS55112037A (en) 1979-02-19 1979-02-19 Static type mos circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1717979A JPS55112037A (en) 1979-02-19 1979-02-19 Static type mos circuit

Publications (1)

Publication Number Publication Date
JPS55112037A true JPS55112037A (en) 1980-08-29

Family

ID=11936713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1717979A Pending JPS55112037A (en) 1979-02-19 1979-02-19 Static type mos circuit

Country Status (1)

Country Link
JP (1) JPS55112037A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979493A (en) * 1982-10-29 1984-05-08 Hitachi Micro Comput Eng Ltd Eprom device
JPH03116495A (en) * 1990-06-01 1991-05-17 Hitachi Micro Comput Eng Ltd Eprom device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979493A (en) * 1982-10-29 1984-05-08 Hitachi Micro Comput Eng Ltd Eprom device
JPH0136200B2 (en) * 1982-10-29 1989-07-28 Hitachi Maikuro Konpyuuta Enjiniaringu Kk
JPH03116495A (en) * 1990-06-01 1991-05-17 Hitachi Micro Comput Eng Ltd Eprom device

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