JPS55101188A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS55101188A
JPS55101188A JP693179A JP693179A JPS55101188A JP S55101188 A JPS55101188 A JP S55101188A JP 693179 A JP693179 A JP 693179A JP 693179 A JP693179 A JP 693179A JP S55101188 A JPS55101188 A JP S55101188A
Authority
JP
Japan
Prior art keywords
node
clock
level
gate
phis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP693179A
Other languages
Japanese (ja)
Other versions
JPS6161200B2 (en
Inventor
Akira Osami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP693179A priority Critical patent/JPS55101188A/en
Publication of JPS55101188A publication Critical patent/JPS55101188A/en
Publication of JPS6161200B2 publication Critical patent/JPS6161200B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To cause an output load to be seen small according to output rise by using an insulating gate-type FET to control charging and discharging of required nodes in the inverter which converts the level of a prescribed external clock. CONSTITUTION:The level of the clock of a transistor logical level applied from the external to MOSFETQ3 of an insulating gate-type FET is converted to the level of clock phiS of the MOS transistor from node 2 connected to bootstrap capacity C1F between MOSFETQ2, which has the source connected to power source VDD, and MOSFETQ4, which has the gate connected to node 4 between MOSFETQ4 and Q6. The gate of MOSFETQ6 is connected to MOSFETQ7 and Q8 through node 5 similarly, and node 5 rises according as conversion clock phiS rises, and node 4 is discharged through FETQ6, and FETQ4 becomes almost non-conductive. Consequently, the load capacity is seen small from node 2, so that the rise speed of conversion clock phiS after that can be enhanced.
JP693179A 1979-01-23 1979-01-23 Semiconductor circuit Granted JPS55101188A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP693179A JPS55101188A (en) 1979-01-23 1979-01-23 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP693179A JPS55101188A (en) 1979-01-23 1979-01-23 Semiconductor circuit

Publications (2)

Publication Number Publication Date
JPS55101188A true JPS55101188A (en) 1980-08-01
JPS6161200B2 JPS6161200B2 (en) 1986-12-24

Family

ID=11651984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP693179A Granted JPS55101188A (en) 1979-01-23 1979-01-23 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS55101188A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812348A (en) * 1981-07-15 1983-01-24 Nec Corp Semiconductor circuit
JP2008125558A (en) * 2006-11-16 2008-06-05 Newgin Corp Replenishing gutter for game ball

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354955Y2 (en) * 1984-12-25 1991-12-05

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812348A (en) * 1981-07-15 1983-01-24 Nec Corp Semiconductor circuit
JPH0255974B2 (en) * 1981-07-15 1990-11-28 Nippon Electric Co
JP2008125558A (en) * 2006-11-16 2008-06-05 Newgin Corp Replenishing gutter for game ball

Also Published As

Publication number Publication date
JPS6161200B2 (en) 1986-12-24

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