JPS6161200B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit constructed of semiconductor elements, and particularly to an integrated circuit using an insulated gate field effect transistor.

The following explanation uses a typical MOS transistor (hereinafter referred to as MOST) among insulated gate field effect transistors, and uses an N-channel transistor.
The high level is a logic "1" level and the low level is a logic "0" level. However, circuit-wise, the P channel MOST is essentially the same.

External input clocks for MOS dynamic random access memory (hereinafter referred to as MOS RAM) integrated circuits are all becoming TTL level to facilitate interface with peripheral devices. In this case, an inverter is first required to receive the external input clock and convert it into MOS level internal clock timing. This will be explained below with reference to the drawings. Conventionally, an inverter of the type shown in FIG. 1 has been used in most cases. When the TTL level external clock input _TTL is at a high level, MOST Q3 is conductive, and by setting the current capacity of MOST Q3 to be sufficiently larger than MOST Q2, node 2, that is, the output φ, is
It is at a low level determined by the ratio of current capabilities of MOST Q2 and MOST Q3. Node 1 is MOST Q1
is charged to the (V _DD -threshold voltage) level.
When _TTL goes from high level to low level,
MOST Q3 becomes non-conductive and the output φ begins to rise through MOST Q2, causing the bootstrap capacitor C1F to raise the level at node 1 until it reaches V _DD -threshold voltage +C1F/C1+C1F×V ₂ . Here, C1 is the capacitance of node 1,
V ₂ is the voltage at node 2, that is, the output φ. MOST Q ₂
is driven into the non-saturation region, and the output φ rises to the V _DD level. While _TTL is at a low level, it corresponds to the active operation period, and as the output φ rises, the MOS
RAM read or write operations are performed. Therefore, how the output φ rises greatly affects the operating performance, that is, the speed, and it is required that the ratio of the current capacity of the MOST Q2 to the load capacity of the node 2, that is, the output φ, be as large as possible. MOSTQ
The current capacity of 2 is normally limited by the restrictions imposed by the V _DD power supply current standard (standby current) during the period when _TTL is at a high level, so the load capacitance of output φ must be kept as small as possible. . The load capacitance of output φ is MOST Q2
and the drain of Q3. Source diffusion capacitance and output φ
Consists of the capacity of MOST to which MOST is connected
Q3 requires a sufficiently larger current capacity than MOST Q2, so the dimensions are usually larger and MOST Q
Normally, the ratio of the drain diffusion capacitance No. 3 to the load capacitance of the output φ is the highest. Focusing on this point, a circuit shown in FIG. 2 has been proposed with the aim of improving the rise of the output φ. _TT
Node (V _DD − threshold voltage), node 2 while _L is at high level
and node 3 determines the current capability of the series-connected MOST consisting of MOST Q4 and MOST Q3.
Low level determined by taking a value sufficiently larger than Q2, node 4 is MOST because Q6 is non-conducting.
MOST is at the (V _DD -threshold voltage) level due to Q5.

When _TTL transitions from high level to low level and enters the active period, MOST Q3 becomes non-conductive and MOST
Node 2, that is, output φ, begins to rise through Q2, but MOST Q4 is also conductive, and node 3 follows node 2 and rises. By making the current capacity of MOST Q6 sufficiently larger than that of MOST Q5,
As node 3 rises, node 4 transitions from the (V _DD -threshold voltage) level to a lower level determined by the ratio of the current capabilities of MOSTs Q5 and Q6. Therefore,
MOST Q4 becomes non-conductive during the rise of the output φ, and the capacitance of the node 3 becomes invisible from the output φ. During the period when _TTL is at a high level, the gate of MOST Q4 is at a level (V _DD - threshold voltage) which is higher than _TTL , so the dimensions of MOST Q4 required to maintain the output φ at a low level are:
It can be made much smaller than MOST Q3. Therefore
After MOST Q4 becomes non-conductive, the output φ rises quickly because the drain diffusion capacitance of MOST Q4 is small and the load capacitance is light. That is, the rising waveform of the output φ becomes as shown in Fig. 3,
While MOST Q4 is conducting, in addition to the output φ, the capacitance of node 3 can be seen from MOST Q2, so
The load is the same as in FIG. 1, but after becoming non-conductive, the load capacity is only equal to the output φ, and the speed is increased due to the lighter weight. It is taken advantage of that the capacitance at node 2 in Figure 2 can be much smaller than that at node 2 in Figure 1, but the circuit in Figure 2 dissipates DC current in the path of MOST Q5 and Q6 during low _TTL levels. It has the disadvantage of Furthermore, if the current capacity of MOST Q6 is not sufficiently larger than that of MOST Q5, the speed at which the level of node 4 decreases in response to the rise of node 3 will be delayed, and the time when MOST Q4 will become non-conductive will be delayed. That is, at the rise of the output φ,
How the current capacity of MOST Q5 and Q6 is determined has a major influence.

The purpose of the present invention is to eliminate these drawbacks and to
When the output starts to rise in an inverter that receives a level external clock input and converts it to a MOS level output, the output load immediately appears small, and the subsequent output rises quickly. There is no consumption of
The object of the present invention is to provide a semiconductor circuit in which the size of the MOST can be reduced without any restrictions.

A semiconductor circuit according to the present invention includes a load element having one end connected to a first power supply terminal and the other end connected to a first node;
A first insulated gate field effect transistor (hereinafter referred to as IGFET) has a drain connected to a first node, a gate connected to a second node, and a source connected to a third node; a drain connected to a third node and a gate connected to a TTL level input; a second IGFET having a first clock source connected to a second power supply terminal and a drain connected to the first power supply terminal;
a third clock whose gate is in antiphase with the first clock and whose second clock source is connected to the second node;
IGFET, drain is the second node, gate is the fourth node
node, the fourth whose source is connected to the second power terminal
, and a first impedance switching means connected between the first node and the fourth node and controlled by the second clock.

A circuit configuration diagram of the present invention is shown in FIG. 4, and an operating waveform diagram is shown in FIG. 5. MOST Q2 and _TTL enter the gate to increase the MOS level conversion output φ _S generated in response to _TTL . MOST Q4 is inserted between MOST Q3 as in Figure 2, but the gate level control of MOST Q4 is Differently, in Figure 4
This is done using MOST Q5-Q8. _φE is
Receives _TTL , occurs sufficiently later than φ _S , and _TTL
is the activation timing to maintain the high level while it is at the low level, that is, during the active period. When _TTL is at a high level, node 1 is (V _DD - threshold voltage), nodes 2 and 3 are the current capability of the series connected MOST consisting of MOST Q4 and MOST Q3.
It is at a low level determined by taking a value sufficiently larger than 2. Node 4 was charged to the (V _DD − threshold voltage) level by φ _E during the previous active period, and _TTL
During the reset period when is at a high level, φ _E is at a low level and MOST Q5 becomes non-conductive, but the level at node 4 is maintained dynamically. _E
is a clock having exactly the opposite phase to _φE , and when _TTL is at a high level, it is at the V _DD level, MOST Q7 is conductive, node 5 is at a low level equal to node 2, and MOST Q6 is non-conductive. MOST Q8
is non-conducting with the gate φ _E. When _TTL transitions from high level to low level and enters the active period
MOST Q3 becomes non-conductive and node 2, ie, the output φ _S , begins to rise through MOST Q2.
Through MOST Q7, node 5 rises following φ _S , and when the threshold voltage is exceeded, MOST Q6 becomes conductive, the charge dynamically maintained in node 4 is discharged, and node 4 immediately reaches the ground potential. As a result, MOST Q4 becomes non-conducting and the load capacitance of node 3 is no longer visible from node 2. MOSTQ
The high level of the gate of MOST Q3, that is, the high level of node 4, is (V _DD - threshold voltage), which is increased by the high level of the gate of MOST Q3, that is, the high level of _TTL , and the high level of MOST Q4 that is necessary to maintain the output φ _S at a low level. The dimensions are
It can be made much smaller than MOST Q3. Therefore
The output φ _S rises quickly after MOST Q4 becomes non-conductive because the drain diffusion capacitance of MOST Q4 is small and the load capacitance is light. In response to the output φ _S , activation timing necessary for the operation of the MOS RAM is generated during the low level period of _TTL . If an activation timing φ _E that occurs sufficiently late than φ _S is selected, MOST Q5 and Q8 become conductive due to the rise in φ _E , and _E shifts to a low level.
MOST Q7 becomes non-conductive. As a result, node 5
moves to ground potential, MOST Q6 becomes non-conductive, and node 4 is charged by MOST Q5 to the high level of _E to V _DD (V _DD -threshold voltage).
When _TTL transitions from low level to high level and enters the reset period, MOST Q3 becomes conductive, and together with MOST Q4, which is already conductive, node 2, that is, output φ
Shift _S and node 3 to a lower level. φ _E also φ _S
Then it is reset and moves to ground potential,
MOST Q5 and Q8 become non-conductive and _E rises after _φE reset. At the time MOST Q7 conducts, φ _S is already at a low level and node 5 remains low. Therefore, node 4 is also (V
Since MOST Q5 becomes non-conductive while remaining at the _(DD - threshold voltage) level, the level is dynamically maintained. The operation of the circuit shown in FIG. 4 has been explained above, and although the behavior of the rise of the output φ _S is basically the same as that shown in FIG. 2, the following improvements can be obtained.

(1) MOST Q5 to Q8, which control the gate level of MOST Q4, operate completely dynamically, and there is no path through which direct current flows.

(2) When φ _S rises, node 5 rises almost simultaneously, and when the threshold voltage is exceeded, node 4 is immediately discharged by MOST Q6. That is, when φ _S rises to around the threshold voltage, MOST Q4 is almost non-conducting, and the time when the load capacitance from node 2 to node 3 becomes invisible is effectively accelerated compared to FIG. 2, and as a result, φ _S rises faster.

(3) There are no particular restrictions on the current capacity of MOST Q5 to Q8, and they can be constructed with relatively small dimensions.

A concrete example using the present invention is shown in FIG. 6, and operation waveforms of main nodes are shown in FIG.

Here, the signals A', ' are true complement address signals generated by an address inverter in response to an address signal. FIG. 6 shows a circuit that selects a word line specified by an address input in a dynamic MOS RAM, and generates activation timing for refreshing the contents of the selected memory cell from an external clock input _TTL at TTL level. When _TTL is at high level, node 1 is (V _DD - threshold voltage)
Nodes 2 and 3 are MOST Q4 and MOST Q
The current capacity of a MOST connected in series consisting of 3
It is at a low level determined by taking a value sufficiently larger than MOST Q2. Node 4 is charged to the (V _DD -threshold voltage) level by activation timing SE in the previous activation period, and while _TTL is at a high level,
SE becomes low level and MOST Q5 becomes non-conductive, but the level of node 4 remains dynamically maintained. If _{the TTL} high level period is long, there is a risk that the charge at node 4 will be discharged due to _leakage current and the level will drop. It supports the level of node 4. The current capacity of MOST Q11 is set to be small enough not to affect circuit operation. Node 6 is at (V _DD - threshold voltage) level due to MOST Q9 and MOST
Q7 is conductive, node 5 is at a low level equal to node 2, and MOST Q6 is non-conductive. MOSTQ
8 and Q10 have low SE and are non-conductive.
When _TTL transitions from high level to low level and enters the active period, MOST Q3 becomes non-conductive and MOST
Node 2 begins to rise through Q2. MOSTQ
7, node 5 follows node 2 and rises,
When the threshold voltage is exceeded, MOST Q6 becomes conductive and node 4 immediately goes to ground potential. The current capacity of MOST Q11 is assumed to be small enough not to affect the response of node 4 at this time. At this point, the capacitance from node 2 to node 3 is no longer visible, and thereafter the rise at node 2 becomes steeper as the load becomes lighter. Due to the rise of node 2, node 7 increases through MOST Q12 (V
_DD − threshold voltage) level and MOST Q1
6's current capacity is sufficiently larger than MOST Q15,
P moves to a lower level. After this, node 10 becomes
Rising through MOST Q17, MOST Q19
The circuit response of ~Q22 reaches V _DD -threshold voltage + C10 _F /C10 + C10 F x V ₁₂ . Here, C10 is the capacitance of node 10, and _V12 is the voltage of node 12. MOST Q23
is driven into the non-saturation region and AE rises to V _DD . AE is the address. Inverter. Each address corresponds to the address input at the activation timing to drive the buffer. Inverter. The address output A' or ' increases with the buffer. As the address output rises, the node 14 shifts to the ground potential, and in synchronization with this, decoder selection and non-selection operations are performed. When MOST Q30 becomes non-conductive, it is already
Node 15 at ( _VDD - threshold voltage) level through MOST Q28 boots. Strap capacity C1
By 5F, the voltage increases to V _DD -threshold voltage + _C15F /C15+C15F× _V16 . Here, C15 is the capacitance of node 15, and _V16 is the voltage of node 16. MOST Q3
1 is driven into the non-saturation region and RA rises to V _DD . Following RA, the word line connected to the selected decoder rises, and the information of the selected memory cell appears on the digit line. Due to the increase in RA, node 20
As the voltage increases, the circuits of MOST Q34 to Q37 respond, and node 19 shifts to ground potential.
When MOSTQ 40 becomes non-conducting, node 20 reaches the next level.

V _DD −threshold voltage + C20 _F /C20 + C20 F×V ₂₁ where C20 is the capacitance of node 20 and V ₂₁ is the voltage of node 21. MOST Q41 is driven into the non-saturation region and SE rises to _VDD . SE activates the sense amplifier connected to the digit line, and the information in the selected memory cell is refreshed. This completes the required activation operation, but SE
In response to the rise in , MOST Q10 becomes conductive, and node 6, which was dynamically maintained at the level of the following equation, is discharged and immediately reaches the ground potential.

V _DD −threshold voltage + C6 _F /C6 + C6 F×V ₅ where C6 is the capacitance of node 6 and V ₅ is the voltage of node 5. MOST Q7 becomes non-conductive.
Since MOST Q8 becomes conductive due to SE, node 5 also moves to ground potential. When MOST Q6 becomes nonconductive, node 4 is charged to the (V _DD -threshold voltage) level through MOST Q5, ready for the reset period. _TTL transitions from low level to high level and resets. When entering the pre-charge period
MOST Q3 and Q13 conduct, causing nodes 2 and 3 to go low and then node 7 to ground potential. When MOST Q16 becomes non-conductive, P becomes
MOST begins to rise through Q15 and node 8 rises to V _DD - threshold voltage + C8 _F /C8 + C8F x V ₉ due to the boot strap capacitance C8F, driving MOST Q15 into the non-saturation region and P to the V _DD level. Rise. Here C8
is the capacitance of node 8 and V ₉ is the voltage of node 9. As P rises, all activation timings are reset, and various parts of the circuit are reset. A pre-charge is carried out. At this time
MOST Q9 also conducts and node 6 rises to the (V _DD -threshold voltage) level, but node 5 goes to a low level equal to node 2 and MOST Q6 remains non-conducting. Node 4 is determined by MOST Q5 (V _DD −
(threshold voltage) level and MOST Q11 works to prevent level attenuation. The circuit operation of the specific embodiment shown in FIG. 6 has been described above, but since node 2 is the generation source, the rise characteristic of the activation timing is greatly influenced by how it rises. When node 2 rises and exceeds the threshold voltage, MOST Q4 becomes non-conductive, and thereafter node 2 rises steeply, which is very effective in obtaining high-speed operation.

As described above, according to the present invention, as soon as the output of an inverter that receives a TTL level external clock input and converts it to a MOS level output begins to rise, the output load appears small near the threshold voltage, and the subsequent output A circuit with a high rate of rise can be operated at low power without consuming direct current, and
The size of MOST can also be realized with a configuration that can be made smaller without any restrictions.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the basic inverter configuration that converts TTL level input to MOS level output.
Figure 2 is a circuit diagram showing a conventional example that can speed up the rise of the MOS level output converted from TTL input, Figure 3 is its operating waveform diagram, and Figure 4 is an improvement based on the same idea as Figure 2. FIG. 5 is a basic circuit diagram of the present invention, and FIG. 5 is an operating waveform diagram thereof, FIG. 6 is a circuit diagram showing a specific embodiment of the present invention, and FIG. 7 is an operating waveform diagram thereof. Symbols in the figure: Q1 to Q43...MOS transistors, C1F to C20F...boot. Strap capacitance, V _DD ... power supply.

Claims (1)

[Claims] 1 A load element whose one end is connected to a first power supply terminal and the other end to a first node, and a first insulated gate type whose drain is connected to the first node, the gate is connected to the second node, and the source is connected to the third node. A field effect transistor, a second insulated gate field effect transistor whose drain is connected to a third node, whose gate is connected to a first clock of TTL level input, and whose source is connected to a second power supply terminal, and whose drain is connected to the first power supply terminal. , the gate rises later than the fall of the first clock;
When the second clock falls in response to the rise of the clock, a third insulated gate field effect transistor is connected, the source of which is connected to the second node, the drain of which is connected to the second node, the gate of which is connected to the fourth node, and the source of which is connected to the fourth node. A fourth insulated gate field effect transistor is connected to the power supply terminals of the second clock, and the drain is connected to the first node, the gate is connected to a third clock having an opposite phase to the second clock, and the source is connected to the fourth node. and a sixth insulated gate field effect transistor whose drain is connected to the fourth node, whose gate is connected to the second clock, and whose source is connected to the second power supply terminal. The semiconductor circuit includes: the second node is discharged at the falling edge of the first clock, and the second node is charged during a period when the first clock is at a low logic level.