JP2580226B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and is used, for example, in a dynamic RAM (Random Access Memory) incorporating a substrate back bias voltage generation circuit. It concerns particularly effective technologies.

[Conventional technology]

Like a dynamic RAM, a MOSFET (Metal Oxide O
xide Semiconductor Field Effect Transistor), the application of an appropriate negative substrate back bias voltage to the semiconductor substrate reduces the parasitic capacitance between the substrate and each circuit element, This is an effective means for controlling the threshold voltage. The substrate back bias voltage is formed by a substrate back bias voltage generation circuit built in a dynamic RAM or the like.
Thus, for example, a single power supply can be achieved with a power supply voltage V _CC of +5 V, and the number of external terminals can be reduced.

A dynamic RAM incorporating a substrate back bias voltage generation circuit is described in, for example, Japanese Patent Application Laid-Open No. 55-13566.

[Problems to be solved by the invention]

In the conventional dynamic RAM and the like described above, the substrate back bias voltage is set to a negative voltage as described above, and its absolute value is controlled to be small and precisely in order to increase the effective gate length of the MOSFET. Is considered effective. For this reason, the substrate type back bias voltage generating circuit of the dynamic RAM is provided with, for example, a level determination circuit LVD as shown in FIG.

In FIG. 4, a substrate back bias voltage generation circuit VB
The G level determination circuit LVD is a P level provided in series between the power supply voltage V _CC of the circuit and the substrate back bias voltage V _BB.
It includes a channel MOSFET Q2 and N-channel MOSFETs Q15 and Q16. MOSFET Q2 is always on by its gate being coupled to the ground potential of the circuit. Also, MOSFET Q1
The gate of 5 is coupled to the ground potential of the circuit and the MOSFET Q16
Is formed into a diode by connecting its gate and drain. MOSFETQ15 and Q16 are designed to have the same threshold voltage V _{TH N.}

Substrate back bias voltage V _BB is shallow, the absolute value thereof is, | V _BB | when are <2 × V _{TH N,} MOSFETQ15 and Q16 are turned off. Therefore, the level of the detection node n6 to which the input terminal of the inverter circuit N5 is coupled becomes high level, and the output signal of the inverter circuit N6 becomes high level. Therefore, the reference pulse signal so formed by the oscillation circuit OSC is transmitted to the charge pump circuit CP, and the substrate back bias voltage _VBB is gradually increased.

Substrate back bias voltage V _BB is deepened, the absolute value thereof is, | V _BB |> If the 2 × V _{TH N,} MOSFETQ15 and Q16 are turned on. Therefore, the level of the detection node 6 is set between the MOSFETs Q2 and Q15.
And a predetermined low level determined by the conductance ratio of Q16 and the output signal of the inverter circuit N6 becomes low level. Therefore, the reference pulse signal so is not transmitted,
The charge pump circuit CP stops its boosting operation. Thus, the substrate back bias voltage V _BB, the absolute value is controlled to a value close to the 2 × V _{TH N.}

However, it has been clarified by the present inventors that such a substrate back bias voltage generation circuit VBG has the following problems. That is, the level determination circuit LVD of the substrate back bias voltage generation circuit VBG is, as described above, a P-channel MOS provided in series between the circuit power supply voltage V _CC and the substrate back bias voltage V _BB.
Includes FET Q2 and N-channel MOSFETs Q15 and Q16. These MOSFETs have a substrate back bias voltage V _BB of 2 × V _TH
When it is deeper than _N , it is simultaneously turned on, and a through current flows between the power supply voltage V _CC of the circuit and the substrate back bias voltage V _BB . Therefore, MOSFET Q2 of level judgment circuit LVD
The conductance is reduced to such an extent that the magnitude of the through current does not matter. However, MOSFET Q2
When the MOSFETs Q15 and Q16 are turned off, the time required for the charging operation of the detection node n6 increases because the conductance of the detection node n6 is reduced. Therefore, the response speed of the level determination circuit LVD becomes slow, and a shallow and stable substrate back bias voltage _VBB cannot be obtained. This increases the gate length of the MOSFET constituting the dynamic RAM or the like equivalently, which is a factor that hinders high-speed operation.

An object of the present invention is to provide a substrate back bias voltage generating circuit capable of supplying a shallow and stable substrate back bias voltage. Another object of the present invention is to provide a MOSFET which constitutes a semiconductor integrated circuit device such as a dynamic RAM.
Of the present invention is to shorten the gate length and speed up the operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
The level determining circuit of the substrate back bias voltage generating circuit performs the level determining operation of the substrate back bias voltage in synchronization with the reference pulse signal. According to the result, the boosting operation of the charge pump circuit is performed every cycle of the reference pulse signal. Is to be performed selectively.

[Action]

According to the above-described means, the time during which a through current flows in the level determination circuit is shortened, and the precharge
Since the conductance of the MOSFET can be increased, the response speed can be increased and a shallow and stable substrate back bias voltage can be formed while reducing the power consumption of the substrate back bias voltage generation circuit. As a result, MOS such as a dynamic RAM incorporating a substrate back bias voltage generation circuit
The gate length of the FET can be shortened and the operation speed can be increased.

〔Example〕

FIG. 3 shows a dynamic RA to which the present invention is applied.
A block diagram of one embodiment of M is shown. The circuit elements constituting each circuit block in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique.

In the dynamic RAM of this embodiment is not particularly limited, since the substrate back bias voltage V _BB of, for example, about -1.5V in the semiconductor substrate is provided, the parasitic capacitance between the substrate and the circuit element is reduced, also The threshold voltage of the MOSFET is controlled. In this embodiment, the substrate back bias voltage V _BB is based on the power supply voltage V _{CC of the} circuit, and the substrate back bias voltage generation circuit V
Formed by BG. The substrate back bias voltage generation circuit VBG includes a level determination circuit LVD that determines the level of the substrate back bias voltage _VBB in synchronization with a reference pulse signal output from the oscillation circuit, and an output of the level determination circuit LVD. It includes a charge pump circuit CP of performing the boost operation of the substrate back-bias voltage V _BB by the reference pulse signal selectively according to the signal. For this reason, in the substrate back bias voltage generation circuit VBG of this embodiment, the conductance of the P-channel MOSFET of the level determination circuit is increased, and the precharge operation of the detection node is speeded up. Therefore, the response speed of the substrate back bias voltage generation circuit VBG can be increased while reducing power consumption, and a shallow and stable substrate back bias voltage _VBB can be formed.

In FIG. 3, a dynamic RAM includes two sets of memory arrays MARY0 and MARY1 arranged symmetrically and a sense amplifier SAP provided corresponding to these memory arrays.
0, SAP1 and SAN0, SAN1, and column switches CS0 and CS
Including 1.

The memory arrays MARY0 and MARY1 are composed of m + 1 word lines arranged in the vertical direction and n + 1 word lines arranged in the horizontal direction.
Each set includes complementary data lines and (m + 1) × (n + 1) dynamic memory cells arranged in a grid at the intersections of these word lines and complementary data lines.

The word lines forming the memory arrays MARY0 and MARY1 are:
It is coupled to the corresponding row address decoders RAD0 and RAD1, and is alternatively selected.

A predetermined predecode signal is supplied from the prerow address decoder PRAD to the row address decoders RAD0 and RAD1. The row address decoders RAD0 and RAD1 supply the memory arrays MARY0 or MARY0 according to these predecode signals.
The word line corresponding to ARY1 is alternatively set to a high level selected state.

Although not particularly limited, the pre-row address decoder PRAD includes i-bit complementary internal address signals a x0 to a xi-1 except for the most significant bit from the row address buffer RAB (here, for example, the non-inverted internal address signal ax0 and the inverted Complementary internal address signal with internal address signal ▲ ▼
expressed as a x0. The same applies hereinafter). Further, a timing signal φx is supplied from a timing generation circuit TG described later. The pre-row address decoder PRAD is selectively activated by the timing signal φx being set to a high level. In this operating state, the pre-row address decoder PRAD outputs the complementary internal address signal a
The x0~ a xi-1 is decoded in a predetermined combination, and forming the pre-decode signal, a row address decoder RAD
To supply.

The row address buffer RAB holds the row address signal supplied via the address multiplexer AMX, on the basis of these row address signals, forming the complementary internal address signals a x0~ a xi.

The address multiplexer AMX selects the X address signals AX0 to AXi supplied via the external terminals when the dynamic RAM is in the normal operation mode and the timing signal φref is at the low level, and the row address buffer RAB
To communicate. When the dynamic RAM is set to the refresh mode and the timing signal φref is set to the high level, the refresh address signals ar0 to ari supplied from the refresh address counter RFC are selected and transmitted to the row address buffer RAB.

The refresh address counter RFC performs an advance operation in accordance with the timing signal φrc supplied from the timing generation circuit TG, and the refresh address signals ar0 to ari
To form

On the other hand, the complementary data lines constituting the memory arrays MARY0 and MARY1 are connected to the sense amplifiers SAP0 and SA0 on one side.
It is coupled to the corresponding unit circuit of P1. On the other side, it is coupled to the corresponding unit circuits of the sense amplifiers SAN0 and SAN1, and further coupled to the corresponding unit circuits of the column switches CS0 and CS1.

The sense amplifiers SAP0 and SAP1 have (n + 1) provided corresponding to respective complementary data lines of the memory arrays MARY0 and MARY1.
Unit circuits. When the timing signal φpa is at a high level, the common source line SP
The power supply voltage V _{CC of the} circuit is supplied via the power supply. Similarly, the sense amplifiers SAN0 and SAN1 are connected to the memory arrays MARY0 and MAR1.
It includes n + 1 unit circuits provided corresponding to Y1. When the timing signal φpa is at a high level, the ground potential of the circuit is supplied to these unit circuits via the common source line SN.

The unit circuits of the sense amplifiers SAP0 and SAP1 and the corresponding unit circuits of the sense amplifiers SAN0 and SAN1 each constitute one unit amplifier circuit. These unit amplifier circuits are selectively activated when the timing signal φpa is set to a high level. In this operation state, each unit amplifier circuit amplifies the minute read signal output from the (n + 1) memory cells coupled to the selected word line of the memory arrays MARY0 and MARY1 via the corresponding complementary data line, It is a high level or low level binary read signal.

Although the column switches CS0 and CS1 are not particularly limited,
It includes n + 1 unit circuits provided corresponding to the respective complementary data lines of the memory arrays MARY0 and MARY1. These unit circuits, each complementary data lines of the memory array MARY0 and MARY1 and write complementary common data lines W IO0L, W IO1L or W IO0R,
W IO1R (where, for example, non-inverted signal WIO0L an inverted signal line ▲ ▼ a combined write complementary common data lines W
Expressed as IO0L. Hereinafter the same). These N-channel MOs
The SFET has its gate commonly connected to the gate of a similar N-channel MOSFET of an adjacent unit circuit, and the corresponding write data line selection signal YW from the column address decoder CAD.
By supplying 0, YW2 to YWn-1, each functions as a switch MOSFET. This allows the memory array
Each complementary data line of MARY0 and MARY1 is a dynamic RA
When M is in the write mode and the corresponding write data line selection signals YW0, YW2 to YWn-1 are alternatively set to high level, two pairs are selected, and the write complementary common data lines W IO0L, W IO1L or W IO0R, is selectively connected to the W IO1R.

Further, each unit circuit of the column switches CS0 and CS1 is
It is not particularly limited, including a ground potential of the circuit and the read complementary common data lines R IO0L, R IO1L or R IO0R, two pairs of N-channel MOSFET provided in series between the R IO1R.
Among these, the pair of N-channel MOSFETs function as amplification MOSFETs by coupling their gates to the non-inverted signal line and the inverted signal line of the corresponding complementary data lines of the memory arrays MARY0 and MARY1, respectively. The other pair of N-channel MOSFETs are connected to one of the adjacent unit circuits of the unit circuit.
The gates of the pair of N-channel MOSFETs are commonly coupled, and function as switch MOSFETs by receiving corresponding read data line selection signals YR0, YR2 to YRn-1 from the column address decoder CAD, respectively. As a result, the complementary data lines of the memory arrays MARY0 and MARY1 are set so that the dynamic RAM is in the read mode and the corresponding read data line selection signals YR0, YR2 to YRn-1 are alternatively set to the high level. Two pairs are selected and selectively connected to the read complementary common data lines R IO0L and R IO1L or R IO0R and R IO1R.

Although the column switches CS0 and CS1 are not particularly limited,
The memory array includes n + 1 precharge circuits provided corresponding to the respective complementary data lines of the memory arrays MARY0 and MARY1. These precharge circuits are selectively activated according to the timing signal φpc, and the memory arrays MARY0 and MARY1
Are set to the half precharge level.

The column address decoder CAD is supplied with a predetermined predecode signal from the precolumn address decoder PCAD. According to these predecode signals, the column address decoder CAD reads the read data line select signals YR0,
YR2 to YRn-1 or write data line selection signals YW0, YW
2 to YWn-1 are alternatively set to a high level selection state.

Although not particularly limited, the pre-column address decoder PCAD supplies j-bit complementary internal address signals a y0 to a yj−1 excluding the most significant bit from the column address buffer CAB.
And a timing signal φy is supplied from the timing generation circuit TG. Pre-column address decoder PCAD
Are selectively activated when the timing signal φy is set to the high level. In this operating state, the pre-column address decoder PCAD decodes the complementary internal address signals a y0 to a yj−1 in a predetermined combination, forms the pre-decode signal, and supplies the pre-decode signal to the column address decoder CAD.

The column address buffer CAB is provided with j + 1-bit Y address signals AY0 to AY0 supplied via external terminals AY0 to AYj.
Yj is held, and based on these Y address signals, the complementary internal address signals a y0 to a yj are formed.

Read Read complementary common data lines R IO0L and R IO0R
And write complementary common data lines W IO0L and W IO0R
Is coupled to the main amplifier MA0. Similarly, the read complementary common data lines R IO1L and R IO1R and the write complementary common data lines W IO1L and W IO1R are connected to the main amplifier MA1.
Is combined with

The main amplifiers MA0 and MA1 include, but are not limited to, two read amplifiers and two line amplifiers.

Although not particularly limited, the read amplifiers of the main amplifiers MA0 and MA1 are commonly connected to a timing signal φra from the timing generation circuit TG. These read amplifiers
When the timing signal φra is a high level, it is alternatively operating state in accordance with the complementary internal address signals a xi of the most significant bits supplied from the column address buffer CAB. In this operating state, each read amplifier
The data input / output circuit further amplifies the binary read signal output from the selected memory cells of the memory arrays MARY0 and MARY1 via the corresponding read complementary common data line.
Communicate to I / O.

On the other hand, the write amplifiers of the main amplifiers MA0 and MA1
Although not particularly limited, the timing signal φwa is commonly supplied from the timing generation circuit TG. These write amplifier, the timing signal φwa is when it is at high level, are alternatively operating state in accordance with the complementary internal address signals a xi of the most significant bits supplied from the column address buffer CAB. In this operation state, each write amplifier forms a complementary write signal according to the output signal wm of the data input / output circuit I / O. These complementary write signals are transmitted to the selected memory cells of the memory arrays MARY0 and MARY1 via the corresponding write complementary common data lines.

The data input / output circuit I / O includes, but is not limited to, a data input circuit and a data output circuit. Further, in the complementary output signal m o0 (here supplied from the main amplifier MA0, for example, the non-inverted output signal mo0 inverted output signal ▲
Together with ▼, it is represented as a complementary output signal m o0. Hereinafter the same) and includes an output selection circuit for transmitting selectively the data output circuit the complementary output signal m o1 supplied from the main amplifier MA1. Of these, the data output circuit is supplied with the timing signal φoe from the timing generation circuit TG,
The output selection circuit is supplied with the complementary internal address signal a yj of the most significant bit from the row address buffer RAB.

When the dynamic RAM is set to the write mode, the data input / output circuit of the data input / output circuit I / O converts the ECL level or TTL level write data supplied via the data input / output terminal DIO into a MOS level write signal. Convert to These write signals are commonly supplied to the write amplifiers of the main amplifiers MA0 and MA1 as the output signal wm.

On the other hand, the output selection circuit of the data input / output circuit I / O connects the complementary output signal lines m o0 and m o1 supplied from the read amplifiers of the main amplifiers MA0 and MA1 to the complementary internal address signals a yj
To the data output circuit selectively.

The data output circuit of the data input / output circuit I / O is selectively activated by the timing signal φoe being at a high level. In this operation state, the data output circuit sends a read signal output via the output selection circuit from the data input / output terminal DIO.

The timing generating circuit TG forms the various timing signals based on a chip enable signal 信号, a write enable signal ▼, an output enable signal ▼, and a refresh control signal ▼, which are supplied as control signals from the outside. , And is supplied to each circuit of the dynamic RAM.

The substrate back bias voltage generation circuit VBG is connected to the external terminal VCC.
A substrate back bias voltage _VBB is formed on the basis of a power supply voltage V _CC of a circuit supplied through the circuit. The substrate back bias voltage V _BB is, for example, a negative voltage such as -1.5V, is supplied to the semiconductor substrate of the dynamic RAM.

FIG. 1 is a circuit diagram showing one embodiment of the substrate back bias voltage generation circuit VBG of the dynamic RAM shown in FIG. In the figure, the channel (back gate)
MOFSEF with an arrow added to the part is a P-channel type,
An arrow is displayed differently from an N-channel MOSFET to which no arrow is added.

In FIG. 1, a substrate back bias voltage generation circuit VB
G includes, but is not limited to, an oscillation circuit OSC, a level determination circuit LVD, and a charge pump circuit CP.

Although not particularly limited, the oscillation circuit OSC has a basic configuration of a ring oscillator and forms a reference pulse signal sa having a predetermined frequency. The reference pulse signal sa output from the oscillation circuit OSC is supplied to the delay circuit DL1 and also to one input terminal of the NAND gate circuit NAG1 and the NOR gate circuit NOG1 forming a combinational circuit. In addition,
The delay circuit DL1 and the combination circuit are included in the oscillation circuit OSC.

The delay circuit DL1 delays the reference pulse signal sa output from the ring oscillator of the oscillation circuit OSC by the delay time td. The output signal of the delay circuit DL1 is
The signal is inverted by 1 to be a pulse signal sb (first pulse signal). The pulse signal sb is supplied to one input terminal of a NAND gate circuit NAG6 of the charge pump circuit CP described later, and is supplied to the other input terminals of the NAND gate circuit NAG1 and the NOR gate circuit NOG1.

The output signal of the NAND gate circuit NAG1 is normally at a high level, and is selectively at a low level when both the reference pulse signal sa and the pulse signal sb are at a high level. That is, the output signal of the NAND gate circuit NAG1 is a negative pulse signal that is temporarily set to the low level immediately before the falling edge of the pulse signal sb. The output signal of the NAND gate circuit NAG1 is supplied to the gate of the P-channel MOSFET Q1 of the level determination circuit LVD as a pulse signal sc (second pulse signal).

The output signal of the NOR gate circuit NOG1 is normally at a low level, and is selectively at a high level when both the reference pulse signal sa and the pulse signal sb are at a low level. That is, the output signal of the NOR gate circuit NOG1 is a positive pulse signal that is temporarily set to the high level immediately before the rising edge of the pulse signal sb. The output signal of the NOR gate circuit NOG1 is supplied as a pulse signal sd (third pulse signal) to one input terminal of the NAND gate circuits NAG2 and NAG3 of the level determination circuit LVD.

The level determination circuit LVD includes, although not particularly limited, a P-channel MOSFET Q1 and an N-channel MOSFET Q1 provided in series between the power supply voltage V _CC of the circuit and the substrate back bias voltage V _BB.
Includes MOSFETs Q11 and Q12. The pulse signal sc is supplied to the gate of the MOSFET Q1, and the gate of the MOSFET Q11 is coupled to the ground potential of the circuit. MOSFET Q12 is formed into a diode form by coupling its gate and drain. The commonly coupled drains of MOSFETs Q1 and Q11 are coupled to the input terminal of inverter circuit N2 as detection node n1 of level determination circuit LVD. Here, the power supply voltage V _CC of the circuit is not particularly limited, but is a positive power supply voltage such as +5.0 V. Also, MOSFET Q1 has a relatively large conductance, and MOSFETs Q11 and Q12 are designed to have the same threshold voltage V _{TH N1} . Although not particularly limited, the threshold voltage V _{TH N1} is set to about 0.75V.
A MOSFET constituting the inverter circuit N2 is connected to the detection node n1.
The stray capacitance mainly including the gate capacitance is coupled.

As a result, the MOSFET Q1 of the level determination circuit LVD is selectively turned on when the pulse signal sc is at a low level, and the precharge MOSFET for charging the detection node n1 to a high level such as the power supply voltage V _CC of the circuit. Function as The MOSFETs Q11 and Q12 are selectively turned on when the absolute value of the substrate back bias voltage V _BB is | V _BB |> 2 × V _{TH N1,} and the discharge MOSFETs for setting the detection node n1 to a low level are provided. Function as

The output signal of the inverter circuit N2 is supplied to the input terminal of the inverter circuit N3 and the NAND gate circuit
It is supplied to the other input terminal of NAG3. Inverter circuit N3
Is supplied to the other input terminal of the NAND gate circuit NAG2. Output signal n2 of NAND gate circuit NAG2
Is supplied to one input terminal of the NAND gate circuit NAG4. Similarly, the output signal n3 of the NAND gate circuit NAG3 is supplied to one input terminal of the NAND gate circuit NAG5. In the NAND gate circuits NAG4 and NAG5, the other input terminal and output terminal are cross-connected to each other, so that a latch is formed. With this, the NAND gate circuits NAG4 and NAG
G5, together with the NAND gate circuits NAG2 and NAG3, constitute one D-type flip-flop circuit triggered by the pulse signal sd.

The output signal n4 of the NAND gate circuit NAG4 is supplied to one input terminal of the NAND gate circuit NAG6 of the charge pump circuit CP. The pulse signal sb is supplied to the other input terminal of the NAND gate circuit NAG6. NAND gate circuit
The output signal of NAG6 is supplied to inverter circuit N4. The output signal n5 of the inverter circuit N4 is supplied to one electrode of the boost capacitance C1. As a result, the pulse signal sb becomes D
On condition that the type flip-flop circuit is set and the output signal n4 of the NAND gate circuit NAG4 is at a high level, it is selectively transmitted to one electrode of the boost capacitance C1 every cycle.

Between the other electrode of the boost capacitor C1 and the ground potential of the circuit, there is provided an N-channel MOSFET Q13 having its gate and drain coupled to form a diode. Furthermore, between the output node of the other boost capacitor C1 of the electrode and the substrate back bias voltage V _BB is, the N-channel MOSFETQ14 which is likewise diode configuration is provided. These MOSFETs Q13 and Q14 are designed to have, but not limited to, the same threshold voltage V _{TH N2} .
MOSFET Q13 is selectively turned on when the potential of the other electrode of boost capacitor C1 becomes higher than the ground potential of the circuit by the threshold value V _{TH N2} or more. MOSFET Q14 is selectively turned on when the potential of the other electrode of boost capacitor C1 is lower than substrate back bias voltage _{VBB by not} less than its threshold voltage V _{TH N2} .

When the output signal n5 of the inverter circuit N4 is set to the high level such as the power supply voltage V _CC, a high level such as the power supply voltage V _CC is induced by the charge pump acts on the other electrode of boosting capacitor C1. However, the boost capacity C1
When the other electrode of the MOSFET is turned to a high level, the MOSFET Q13 is turned on. Therefore, the level V _C is clamped by the threshold voltage of the MOSFET Q13, and V _C = V _{TH N2} . Next, when the output signal n5 of the inverter circuit N4 changes to a low level such as the ground potential of the circuit, the potential V _C of the other electrode of the boost capacitor C1 decreases by the power supply voltage V _CC , and V _C = (V _CC −V _{TH N2} ). Therefore, the potential of the substrate back bias voltage V _BB is higher than the potential of the other electrode of the boost capacitor C1 by the MOSFET.
Attempts to converge to a voltage higher by the threshold voltage of Q14, ie, V _BB = − (V _CC −2Vth). However, the level of the actual substrate back bias voltage V _BB is controlled by the level determination circuit LVD, and is gradually increased by the charge sharing with the stray capacitance or the like existing on the semiconductor substrate of the dynamic RAM. Is leaked. For this reason, the substrate back bias voltage V _BB is
A gentle vibration waveform centered on the judgment level − (2 × V _{TH N1} ).

FIG. 2 is a timing chart of one embodiment of the substrate back bias voltage generation circuit VBG of FIG. As shown in the figure, the substrate back bias voltage generating circuit of this embodiment
An outline of the operation of VBG will be described.

In FIG. 2, the reference pulse signal sa is a repetitive pulse signal having a predetermined period, and its duty is not particularly limited, but is approximately 50%. Reference pulse signal
The signal sa is delayed by the delay time td of the delay circuit DL1 and further inverted to obtain a pulse signal sb. Pulse signal sc
Is a negative pulse that is temporarily set to a low level only while the reference pulse signal sa and the pulse signal sb are both at a high level. The pulse signal sd is a positive pulse that is temporarily set to a high level only during a period in which both the reference pulse signal and the pulse signal sb are at a low level.

When the pulse signal sb is at a low level, the precharge MOSFET Q1 is turned on in the level determination circuit LVD of the substrate back bias voltage generation circuit VBG. MOSFET Q1 is designed to have a relatively large conductance as described above. For this reason, the level of the detection node n1 is almost at a high level like the power supply voltage of the circuit even when the substrate back bias voltage _VBB is made sufficiently deep. This high level is charged to the gate capacitance and the like of the MOSFET constituting the inverter circuit N2.

When the detection node n1 of the level determination circuit LVD is at a high level, the output signal of the inverter circuit N2 is at a low level, and the output signal of the inverter circuit N3 is at a high level. However, as described above, when the pulse signal sc is at a low level, the pulse signal sd is not simultaneously at a high level. Therefore, the output signal n2 of the NAND gate circuit NAG2
The output signal n3 of the NAND gate circuit NAG3 is kept at the high level, and the D-type flip-flop circuit including the NAND gate circuits NAG2 to NAG5 keeps the state up to that point.

Next, when the pulse signal sc is returned to the high level, the MOSF
ETQ1 turns off. Accordingly, the level of the detection node n1 is a selectively high or low level in accordance with the substrate back bias voltage V _BB. That is, before the substrate back bias voltage V _BB is shallow and its absolute value is before the point P where | V _BB | <2 × V _{TH N1} , the MOSFE of the level determination circuit LVD is
TQ11 and Q12 are turned off. Therefore, the detection node n
The level of 1 holds the high level due to the precharge. Therefore, the output signal of the inverter circuit N2 goes low, and the output signal of the inverter circuit N3 goes high.

In this state, when the pulse signal sd temporarily goes high, the output signal n2 of the NAND gate circuit NAG2 temporarily goes low, and the D-type flip-flop circuit including the NAND gate circuits NAG2 to NAG5 outputs the output signal of the NAND gate circuit NAG4. The set state is set so that n4 becomes high level. Therefore, the pulse signal sb is supplied to the NAND gate circuit NAG6
And the output signal n5 of the inverter circuit N4 is transmitted to the charge pump circuit CP for one cycle through the pulse signal sb.
Becomes high level for one cycle. Thus, the substrate back bias voltage V _BB is, is boosted on the falling edge of the output signal n5 pulse signal sb i.e. inverter circuit N4, is deeply only level in accordance with the charge sharing. As a result, the absolute value of the substrate back bias voltage V _BB at the point P is | V _BB |> 2 × V _{TH N1} .

In the level judgment circuit LVD, the substrate back bias voltage V _BB
As the absolute value of
And Q12 are turned on. For this reason, the potential of the detection node n1 is discharged through these MOSFETs Q11 and Q12, and is set to a low level. As a result, the output signal of the inverter circuit N2 goes high, and the output signal of the inverter circuit N3 goes low. Note that the detection node
The time during which the coupling capacitance of n1 is discharged via the MOSFETs Q11 and Q12 is shorter than the time from when the pulse signal sc is returned to the high level to when the pulse signal sd is brought to the high level.

Next, the pulse signal sd is temporarily set to the high level again. In the level determination circuit LVD, since the output signal of the inverter circuit N2 is at a high level, the NAND gate circuit NA
The output signal n3 of G3 temporarily becomes low level, and the output signal n2 of the NAND gate circuit NAG2 remains at high level. Therefore, the output signal of the NAND gate circuit NAG5 goes high, and the output signal of the NAND gate circuit NAG4 goes low. That is, the D-type flip-flop circuit including the NAND gate circuits NAG2 to NAG5 is a NAND gate circuit.
The reset state is such that the output signal n4 of the NAG4 becomes low level. Therefore, pulse signal sb is not transmitted to charge pump circuit CP in the next cycle, and substrate back bias voltage _VBB is not boosted.

As described above, the dynamic RAM of this embodiment, the substrate back bias voltage generating circuit VBG for supplying the substrate back bias voltage V _BB to the semiconductor substrate is incorporated, whereby, between the substrate and the circuit elements The parasitic capacitance is reduced, and the threshold voltage of the MOSFET is controlled. The substrate back bias voltage generation circuit VBG includes an oscillation circuit OSC, a level determination circuit LVD, and a charge pump circuit CP. In this embodiment, the level determination operation by the level determination circuit LVD is synchronized according to the reference pulse signal, and the boosting operation of the charge pump circuit CP is performed by the level determination circuit LVD.
Is selectively performed every cycle of the reference pulse signal in accordance with the output signal of That is, the detection node of the level detector LVD is precharged at a predetermined timing in each cycle, it is selectively discharged in accordance with the substrate back bias voltage V _BB. As a result, the charging time of the detection node, that is, the time during which a through current flows is reduced, and the conductance of the charging P-channel MOSFET can be relatively increased. As a result, the response speed of the level determination circuit LVD is increased, and a shallow and stable substrate back bias voltage _VBB can be supplied.

As shown in the above embodiment, the present invention relates to a dynamic RA incorporating a substrate back bias voltage generation circuit.
By applying the present invention to a semiconductor integrated circuit device such as M, the following effects can be obtained. That is, (1) The operation of determining the level of the substrate back bias voltage by the level determination circuit of the substrate back bias voltage generation circuit is as follows:
The boosting operation of the charge pump circuit is performed in synchronization with the reference pulse signal.
By selectively performing the operation for each cycle, it is possible to obtain an effect that the time during which a through current flows through the detection node of the level determination circuit can be reduced.

(2) According to the above item (1), the effect is obtained that the conductance of the precharge MOSFET for charging the detection node is relatively increased, and the operation of charging the detection node can be accelerated.

(3) According to the above items (1) and (2), the effect is obtained that the response speed of the level determination circuit can be increased while reducing the power consumption.

(4) According to the above items (1) to (3), a shallow and stable substrate back bias voltage is formed, and the dynamic RA
The effect of being able to supply to a semiconductor substrate such as M is obtained.

(5) According to the above items (1) to (4), it is possible to obtain an effect that the gate length of the MOSFET can be shortened and the operation of a dynamic RAM or the like having a built-in substrate back bias voltage generation circuit can be further accelerated.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, the judgment level of the level judgment circuit LVD is the detection node n
It can be set arbitrarily by increasing or decreasing the number of N-channel MOSFETs provided between 1 and the substrate back bias voltage _VBB . The oscillation circuit OSC may be selectively activated according to the activation state of the dynamic RAM or the level of the substrate back bias voltage _VBB . The substrate back bias voltage generation circuit VBG may be configured by a plurality of voltage generation circuits having different current supply capacities. The time relationship between the levels of the reference pulse signal sa and the pulse signals sb to sd is not particularly limited by this embodiment. In FIG. 3, the dynamic RAM may have four or more sets of memory arrays, or may employ an address multiplex system. further,
Substrate back bias voltage generation circuit VBG shown in FIG.
Various embodiments can be adopted, such as a specific circuit configuration of FIG. 1, a block configuration of a dynamic RAM shown in FIG. 3, and a combination of control signals and address signals.

In the above description, the dynamic RA, which is a field of application in which the invention made by the inventor
Although the description has been given of the case where the present invention is applied to M, the present invention is not limited to this. For example, the present invention can be applied to other semiconductor memory devices and various digital integrated circuits. The present invention can be widely applied to at least a semiconductor integrated circuit device having at least a substrate back bias voltage generation circuit.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, the level determination operation of the substrate back bias voltage by the level determination circuit such as the substrate back bias voltage generation circuit is performed in synchronization with the reference pulse signal, and the boosting operation of the charge pump circuit is performed in one cycle of the reference pulse signal according to the result. In this case, the response speed of the level determination circuit can be increased while reducing power consumption. As a result, a shallow and stable substrate back bias voltage can be supplied, so that the gate length of the MOSFET can be reduced and the operation of a semiconductor integrated circuit device such as a dynamic RAM can be further accelerated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a substrate back bias voltage generating circuit of a dynamic RAM to which the present invention is applied, and FIG. 2 is an embodiment of a substrate back bias voltage generating circuit of FIG. FIG. 3 is a block diagram showing an embodiment of a dynamic RAM including the substrate back bias voltage generating circuit of FIG. 1, and FIG. 4 is a substrate back bias voltage generating circuit of a conventional dynamic RAM. FIG. 3 is a circuit diagram showing an example of the embodiment. VBG: substrate back bias voltage generation circuit, OSC: oscillation circuit, LVD: level determination circuit, CP: charge pump circuit, DL1: delay circuit, N1 to N7: CMOS inverter circuit, NAG1 to NAG7 ... NAND gate circuit, NOG1… NOR gate circuit, Q1-Q2… P-channel MOSFET, Q11-Q18…
... N-channel MOSFET, C1-C2 ... Boost capacitance. MARY0, MARY1 …… Memory array, SAP0, SAP1, SAN0, SAN1…
… Sense amplifier, CS0, CS1 …… column switch, CAD ……
Column address decoder, RAD0, RAD1 …… Row address decoder, PCAD …… Pre-column address decoder, PRAD
... pre-row address decoder, CAB ... column address buffer, RAB ... row address buffer, AMX ... address multiplexer, RFC ... refresh address counter, MA0, MA1 ... main amplifier, I / O ... data input / output Circuit, TG: Timing generation circuit.

Claims (1)

(57) [Claims] An oscillation circuit for forming a periodic pulse signal, a pulse formed by the oscillation circuit is supplied through a gate circuit to form a back bias voltage supplied to a substrate, and a power supply voltage. When the substrate potential is set to a predetermined potential, a current flows in synchronism with the pulse signal in a series MOSFET circuit including a MOSFET that is provided between the substrate and the substrate and that is switch-controlled by the pulse signal. And a back bias voltage applied to the substrate by latching an output signal of the level determination circuit in synchronization with the pulse signal and controlling the gate circuit to operate the charge pump circuit intermittently. A substrate back bias voltage generating circuit including a latch circuit for controlling the voltage to a desired voltage. The semiconductor integrated circuit device.