JPS5812348A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To facilitate the manufacture of a semiconductor circuit by a method wherein the high level of the semiconductor circuit output in an active state is increased, the power consumption in a power-down state is brought to zero, and besides, an insulating gate field-effect transistor having special threshold voltage is refrained from using. CONSTITUTION:A transistor T12 is in a non-conductive state when the semiconductor circuit is in power-down state, i.e., the signal to be supplied to the first signal input terminal is at earth level, the output part of the first circuit part becomes Vc level because the transistor T12 is in a non-conductive state, T15 is also in a nonconductive state and the output part of the second partial circuit is placed in Vc level too, and in the third partial circuit, a transistor T16 is in a low impedance state and a transistor T19 is in conductive state, but as the third circuit part is connected to the first signal input terminal through the intermediary of a transistor T17 having the conductive gate 123 of a transistor T18, the potential of the gate 123 is brought to earth level, and the transistor T18 is now in a non-conductive state, thereby allowing the first, the second and the third circuits to consume no electric power at all.

Description

[Detailed description of the invention] The present invention relates to semiconductor circuits.

In a microcomputer with four large memory capacities, one CPU (Central Process
orUnit) It is possible to use more than one memory chip per chip; in this case, the unselected memory chip does not need to be in an active state, so the memory chip is selected by the signal supplied from the CPU. It is common practice to reduce the power consumption of the entire microcomputer system by reducing the power consumption of the microcomputer.

By the way, when the memory chip is selected by the gate circuit used in such a memory chip and the inside of the chip is in an operating state (hereinafter referred to as an active state), it is necessary to drive a large load capacitance at high speed. In a state in which a memory chip is not selected and the power consumption inside the chip is reduced (hereinafter referred to as a power-down state), a gate circuit that consumes little power and outputs a ground level may be required. Conventionally, a circuit shown in FIG. 1 has generally been used as a circuit that satisfies such requirements.

The circuit configuration and circuit operation of the conventional example shown in FIG. 1 when an N-channel insulated gate field effect transistor is used will be explained in detail below. First, a deep W/type insulated gate field effect transistor (hereinafter abbreviated as D-IGFgT) (TI), an enhancement type insulated gate field effect transistor (hereinafter abbreviated as g-IGFgT) (Gl), and a B
- In the first partial circuit composed of IGFgT (T2), the drain /l of (TI) is connected to a constant voltage source, Vc, and the gate 2 and source 3 are both connected to the drain 4 of (G1).
The gate 5 of (Gl) is connected to the second signal input terminal I3, the source 6 is connected to the drain 7 of (T2), and the gate 8 of (T2) is connected to the first signal input terminal !
, the source 9 is grounded, and the source 3 of % (Tl) serves as the output of the first subcircuit. Next, D
- In the second partial circuit composed of IGFRT (T3), B-IGFgT (T4) and E-IOIPET (Ts), the drain lO of % (T3) is connected to the constant voltage source Vc and the source 11 and the source 12. are both (T4) drey/1
3, the gate 14 of (T4) is connected to the output of the first partial circuit, the source 15 is connected to the drain 16 of (Ts), and the gate ↑) 17 of (Ts) is connected to the first signal It is connected to the human power Il, the source 18 is grounded, and the source 12 of (T3) becomes the output of the second subcircuit. Insulated gate field effect transistor (T6), D-IGF
In the third partial circuit composed of BT(TI) and g-IGFgT(Ts), the drain 19 of b(Ts)
is connected to the constant voltage source Vc, and the gate 20 is connected to the first signal input terminal I.
+, the source 21 is connected to the drain /22 of (TI), the gate 23 of % (TI) is connected to the output of the second subcircuit, the source 24 is connected to the drain 25 of (Ts), The gate 26 of Ts) is connected to the output of the subcircuit @l, the source 27 is grounded and the source 24 of (TI)
becomes the output terminal of the third partial circuit and also becomes the output terminal 0 of the entire conventional circuit shown in FIG. First, in the active state, that is, the voltage supplied to the signal input terminal ll of @l is equalized to the voltage value of the constant voltage source Vc, and the voltage level (
(hereinafter referred to as Vc level), Th (T2).

(Ts) and (Ts) are in a conductive state, and when the signal supplied to the second signal input terminal changes from the ground level to the Vc level, (Gl) changes from a non-conductive state to a conductive state. The output of the first partial circuit changes from the Vc level to the ground level, and as a result (T4) changes from a conductive state to a non-conductive state, the output of the second partial circuit rises from the ground level to the Vc level. 4, (T7) changes from high impedance state to low impedance state,
(Ts) changes from a conductive state to a non-conductive state, so a high level appears at output terminal 0, but the high level voltage value a(T
If s) is D-IGFgT, it is Vcv pel, but b(
If Ts) is g-IGFFliT, from the We level (
From this point of view, it is desirable that (Ts) be D-xoi+'g'r.Conversely, in the multi-active state of YaFi, 2
When the signal supplied to the signal input terminal I2 changes from the Vc level to the ground level, (Gl) changes from the conductive state to the non-conductive state, so the output section of the first partial circuit changes from the ground level to the Vc level. , (T4) changes from a non-conducting state to a conducting state, the output section of the second partial circuit changes from Vc level to ground level D, ('I7') changes from a low impedance state to a high impedance state,
(Ts) changes from a non-conductive state to a conductive state, so the output terminal 0 becomes the ground level. Next, in the power-down state, that is, when the signal supplied to the first signal input terminal Il is at ground level, %cI'2)-(Ts) becomes non-conductive, so that the output section of the first partial circuit The potential and the potential of the output part of the second partial circuit are both at Vc level, and L (T7) is in a low impedance state and 1T8)ti is in a conductive state, but (Ts) is because the potential of the gate 20 is at the ground level. Since (Ts) is in a high impedance state or non-conductive state, the output terminal O is at the ground level. However, at this time, if % (Ts) is E-IGFfiT, it is in a non-conducting state, so no current flows in the third partial circuit, and therefore the first
In the power-down state of the entire conventional circuit in the figure, there is no power consumption, but if σ6) is D-IGFgT, even though it is in a high impedance state, current flows through the third partial circuit, resulting in a low power state. However, it is undesirable to consume power, and in the active state, it is preferable that (Ts) be D-IGFgT.
In the Wardau/state, it is preferable for (Ts) to be Fli-IGFBT.Therefore, there are conflicting requirements.
Ts) is normally an insulated gate field effect transistor with a threshold of about 0 volts. However, in the conventional circuit shown in FIG. 1, when the threshold voltage of (Ts) moves to the depletion side, the power consumption in the power down state increases, and when it moves to the enhancement side, the power consumption at output terminal 0 in the active state increases. Since the 1I level is lowered, the permissible range of the II value voltage of (Ts) is extremely narrow, which has been an obstacle in circuit design and in the manufacture of integrated circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor circuit that has a large output voltage at a high level in an active state, consumes no power in a power-down state, and is easy to design without any manufacturing problems.

A semiconductor circuit according to the present invention includes a first insulated gate field effect transistor of a deep drain type, in which a drain is connected to a constant voltage source, a gate and a source are connected to each other; a gate is connected to a first signal source; a second insulated gate field effect transistor of the enhancement type which is grounded; and at least one transistor inserted between the source of the first insulated gate field effect transistor and the drain of the second insulated gate field effect transistor. a first partial circuit constituted by at least one enhancement type insulated gate field effect transistor connected in series and parallel and having at least one input terminal; a drain connected to the constant voltage source; a degree-type third insulated gate field effect transistor whose sources are connected to each other; and an enhancement type fourth insulated gate field effect transistor whose drain is connected to the source of the third insulated gate field effect transistor. a fifth insulated gate field of Ennosummet type, the drain of which is connected to the source of the fourth insulated gate field effect transistor, the gate of which is connected to the first signal source, and the source of which is grounded; and a second partial circuit consisting of an effect transistor.

a sixth insulated gate field effect transistor having a drain connected to the constant voltage source; a sixth insulated gate field effect transistor having a drain connected to the constant voltage source; /T-type seventh insulated gate field effect transistor and drain? IJ: an eighth insulated gate field effect transistor of the construction type, the eighth insulated gate field effect transistor having a gate connected to the source of the sixth insulated gate field effect transistor and having a gate connected to the drain of the seventh insulated gate field effect transistor; a ninth insulated gate field effect transistor of the enhancement type whose drain is connected to the source of the eighth insulated gate field effect transistor and whose source is grounded; The third insulated gate field effect transistor is connected to the gate of the nine insulated gate field effect transistors and is configured by the first O insulated gate field effect transistor of the nine dipleg 1 type.
(1) The source of the @l insulated gate field effect transistor of the first partial circuit is connected to the gate of the fourth insulated gate field effect transistor of the second partial circuit, and Said @1 of the third partial circuit
0 of the third insulated gate field effect transistor of the second subcircuit, and the source of the third insulated gate field effect transistor of the second subcircuit is connected to the sixth insulated gate field of the third subcircuit. a semiconductor circuit connected to the gate of the effect transistor and having the source of the eighth insulated gate field effect transistor of the third partial circuit as an output terminal; and (2) the first insulation of the @10 partial circuit. A source of the gate field effect transistor is connected to the gate of the fourth insulated gate field effect transistor of the second subcircuit and to the gate of the @6 insulated gate field effect transistor of the third subcircuit. and said second
The source of the third insulated gate field effect transistor of the third subcircuit is connected to the drain of the tenth insulated gate field effect transistor of the third subcircuit; This is a semiconductor circuit whose output terminal is the source of an insulated gate field effect transistor.

FIGS. 2 and 3 show implementations of the semiconductor circuit of the present invention. The circuit of the embodiment shown in FIG. 2 is a circuit in which the input signal and the output signal are in the same phase in the active state, and has the same function as the conventional circuit of FIG. The output signal will be in reverse phase. Below, in order to facilitate comparison with the conventional circuit shown in FIG. 1, the configuration and operation of the circuit of the present invention will be explained in detail using the circuit of the embodiment shown in FIG. 2.

The drain 101 of the D-IGFBT ('I'll) is connected to the constant voltage source Vc, the gate 102 and the source 103 are connected to the drain/104 of the E-IGi''hT (G2), and the gate 105 of (G2) Second signal input terminal I2
and the source 106 is F,-IGFET (Tt2
) is connected to the drain 107 of (T12), and the gate 1 of (T12)
0B is connected to the first signal input terminal I8, and the source 10
9 is grounded, (T11), (G2) and (T
12) constitutes a first partial circuit, and the source 103 of (Tll) serves as an output section of the first partial circuit. This first partial circuit has the same configuration and performs the same operation as the first partial circuit in the conventional circuit shown in FIG. D-
The drain 110 of IGFET (Tt3) is a constant voltage source Vc
The gate 111 and the source 112 are connected to B-I.
The gate 114 is connected to the drain 113 of the GFRT (T14), the gate 114 is connected to the output of the first subcircuit, the source 115 is connected to the drain 116 of the H-IGFET (T15), and the gate (T15) 117 is connected to the drain 113 of the GFRT (T14). It is connected to the first signal input terminal 11, and the source 118 is grounded.
(T 13 ), fix4) and (T15) constitute a second partial circuit, and the source of (T13) serves as the output section of the second partial circuit. This second partial circuit also has the same configuration and performs the same operation as the second partial circuit in the conventional column circuit of FIG. The drain/119 of D-IGFgT (T16) is connected to the constant voltage source Vc, and the gate 12
0 is connected to the output of the second subcircuit and the source 121
is connected to the drain 122 of g-IGFWT (T18), and the gate 123 of (T18) is connected to g-IGFgT (TI
? ) is connected to the drain 127 of the source 124 B-
Connected to the drain 131 of IGFBT (T19), (
TI? ) has a gate 126 connected to a constant voltage source Vc, a source 125 connected to a first signal input terminal Che, and (T
The gate 132 of the D-IGFET (T20) is connected to the source 130 of the D-IGFET (T20), and the source 133 is grounded.
The drain 128 and gate 129 of 20) are both connected to the output of the first partial circuit (T16).

(T17), (T18), (T19) and ('I20
) constitutes the third partial circuit ft. In the active state, that is, when the voltage supplied to the signal input terminal I□ of @l is at Vc level, (T12) and (T15) are in a conductive state, and %(T18) gate) 123 has a voltage from w level to (Tl?). Since a voltage subtracted by the threshold voltage of is applied, (T18) is also in a conductive state. Therefore, when the signal supplied to the second signal input terminal I2 changes from the ground level to the VC level in the active state, (G2) changes from the non-conducting state to the conducting state, so that the output section of the first partial circuit is Since the ground level tC changes from the Vc level and (T14) changes from a conductive state to a non-conductive state, the output section of the second partial circuit changes from the ground level to the Vc level. As a result, in the third partial circuit, (T19) changes from a conductive state to a non-conductive state, and (T16) changes from a high impedance state to a low impedance state, so the potentials of the drain 122 and source 124 of (T18) change. Although it rises from the ground level, (T18) is in a conductive state and a channel is formed on the surface of the semiconductor substrate below the gate insulating film, so the potential of the gate 123 of (T18) also increases due to the gate insulating film with the channel part. It rises due to capacitive coupling via . At this time, the threshold voltages of (T17) and (T18) are both Vte, and the coupling capacitance between the gate 123 of (T18) and the channel part via the gate insulating film is Cg, (
T18) is connected to the gate 123 of (T18).
7) The stray capacitance added to the drain is Cs+, and the potential of Vc level is Vc' and ftLij, (Cg/C5))2
C to satisfy the relationship VT/(VC'-2VT)(F)
If the value of g is set, the potential of the gate 123 at (T18) will be greater than Vc"-Vr, and the output terminal O will have Vc.
You can get level output. Next, when the signal supplied to the second signal input terminal I2 in the active state changes from the Vc level to the ground level, the color (G2) changes from the conductive state to the non-conductive state, and the output section of the first partial circuit changes from the ground level to the Vc level, (T14) changes from a non-conducting state to a conducting state9, and the output section of the second partial circuit becomes Vc level.
Since the c level drops to the ground level, (T16) of the partial circuit of sg3 becomes a no-impedance state fi (T
19) changes from a non-conductive state to a conductive state, so the potential of the output terminal O becomes the ground level. At this time, the potential of the drain y122 and source 124 of (TlB) decreases from the Vc level to the ground level, so the gate 1 of (Tl 8 )
The potential of 23 is Vc due to capacitive coupling with the channel part.
It decreases to the level minus the threshold voltage of (T17). Next, in the power down state, that is, when the signal supplied to the first signal input terminal is at the ground level, (T1
2) becomes non-conductive, the output section of the first partial circuit becomes Vc level, and since (T15) also becomes non-conductive, the second
Since the output section of the partial circuit also becomes the Vc level, in the third partial circuit, (T16) is in a low impedance state, (T19) is in a conductive state, but (T18) 12B is in a conductive state. Since it is connected to the first signal input terminal through one (T17), the potential of the gate 123 becomes the ground level, and (T18) becomes non-conductive, so the first partial circuit, the second partial circuit, and the third partial circuit There is no power consumption in any of the partial circuits.

Next, the necessity of the third partial circuit D-IGFgT (T2o) will be described. In a state where the potential of the first signal input terminal 11 and the level of the second signal input terminal are both at the ground level, that is, from the power down state, the potential of the first signal input terminal changes to the Vc level. In other words, when transitioning to the active state, the output terminal 0 changes from the ground level to the Vc level, but at this time, the potential of the first signal input terminal 11 rises from the ground level and m(T
i7), the potential of the gate 132 of (T18) is increased from the Vc level to (T2O) by % (T19) of the time t1 required to raise the gate 123 of (T18) to a potential close to the Vc level minus the threshold voltage of (T17).

Discharge through (G2) and (T12), and (T19)
If the time t for changing from a conductive state to a non-conductive state is longer than 9, even if the potential of the gate 123 rises due to capacitive coupling between the channel part and the gate part (T18), it will not reach the Vc level (T28). The potential of the output terminal O does not reach the potential added by the step voltage, and the potential of the output terminal O does not reach the Vc level. For this purpose, (T20) is inserted and its resistance value is set so that ti≦12, but in actual design, Fi (Tt
If the area of the gate part of s) is made large, it is not necessary to satisfy t1≦t (the resistance value of (T20) can be a small i value, so it will not make the design difficult). -0 As clarified above by showing the circuit of the embodiment shown in Fig. 2, the semiconductor circuit of the present invention is capable of outputting high level C level in the active state, and in the power down state. It is superior to the conventional circuit shown in FIG. 1 in that it consumes no power, and furthermore, it does not use insulated gate field effect transistors with special threshold voltages, making it easy to manufacture integrated circuits including the circuit of the present invention. -ru.

FIG. 3 shows another embodiment of the semiconductor circuit of the present invention; 6. D
- The drain 7201 of IGFET (T21) is a constant voltage source V
The gate 202 is connected to g−c along with the source 203.
Connected to the drain 204 of IGk'BT (G3)%
(G3) is connected to the gate 205 second signal input terminal I2, and the north 206qg-IGF14T (T22)
Connected to O drain 720'l, gate 2 of (T22)
08 is connected to the signal input terminal I of @l, and the source 20
9 is grounded, (T21), (G3) and (T
22).

A first partial circuit is constituted, and the source 203 of (T21) serves as an output section of the first partial circuit.

D-IGFgT('r23)tol”v4y210tj
Constant voltage source VcVc connected) 21 Iff/-,
Dray/2 of E-IGFgT (T24) with X212
13, goo) 214 is connected to the output of the partial circuit @l, and source 215 is connected to 14-IGFfiT
Connected to the drain 216 of (T25), signal input terminal of (T25) 217Fi@1! , connected to −
Here, (T23), (T24), and (T25) constitute the @2 partial circuit t-, and the source of m (Tza) becomes the output part of the @20 partial circuit i. In addition, D-IGFgT (T
26) is connected to the constant voltage source Vc, the gate 220 is connected to the output part of the first partial circuit, and the source 221 is connected to the drain 222 of E-IGFgT (T28).
The gate 223 of (T28) is connected to g-IGFg
Connected to the drain 227 of T (T27) and connected to the source 22
4 is g-IGrj! The gate 226 of (T27) is connected to the constant voltage source Vc, the source 225 is connected to the second signal input terminal I, and the gate 232 of (T29) is connected to the drain /231 of (T29). −IGFgT(
T30) O:/- to 230tCIII! and source 2
33 is grounded, (T30) dray/228 and goo)
229ti are both connected to the output part of the second partial circuit.
% (T26), (T27).

Claims (1)

[Claims] A first insulated gate field effect transistor of a deep four-node type in which the drain is connected to a constant voltage source and the gate and source are connected to each other; and an enhancement type insulated gate field effect transistor in which the gate is connected to the first signal source and the source is grounded. a second insulated gate field effect transistor, and at least one input terminal inserted between the source of the insulated gate field effect transistor and the drain of the second insulated gate field effect transistor. a first partial circuit configured by at least one or more series-parallel-connected insulated gate field effect transistors of type S/S/S/S;
a third insulated gate field effect transistor of the dipleg type, the drain of which is connected to the constant voltage source, the gate and the source of which are connected to each other; and the drain is connected to the source of the third insulated gate field effect transistor. an enhancement type fourth insulated gate field effect transistor; a drain is connected to the source of the fourth insulated gate field effect transistor, a gate is connected to the first signal source, and a source is grounded. No l! 5
a sixth insulated gate field effect transistor of the dipleg WI type, the drain of which is connected to the constant voltage source, and the source of which is connected to the first signal; an enhancement-type seventh transistor connected to the constant voltage source, and having a gate connected to the constant voltage source;
an enhancement-type eighth insulated insulated gate field effect transistor whose drain/is connected to the source of the sixth insulated gate field effect transistor and whose gate is connected to the drain/of the seventh insulated gate field effect transistor; a gate field effect transistor, a ninth insulated gate field effect transistor of an ensment type in which the drain/is connected to the source of the eighth insulated gate field effect transistor and whose source is grounded; Mutual
a third subcircuit constituted by a tenth insulated gate field effect transistor of the dipleg type, the source of which is connected to the gate of the ninth insulated gate field effect transistor; The source of the first insulated gate field effect transistor of the first subcircuit is connected to the gate of the fourth insulated gate field effect transistor of the second subcircuit and the source of the fourth insulated gate field effect transistor of the third subcircuit. 10 insulated gate field effect transistors, and the source of the third insulated gate field effect transistor of the second subcircuit is connected to the sixth insulated gate field effect transistor of the third subcircuit. , and the source of the eighth insulated gate field effect transistor of the partial circuit II3 serves as an output terminal.