JPS5499555A - Transistor circuit - Google Patents

Transistor circuit

Info

Publication number
JPS5499555A
JPS5499555A JP12182978A JP12182978A JPS5499555A JP S5499555 A JPS5499555 A JP S5499555A JP 12182978 A JP12182978 A JP 12182978A JP 12182978 A JP12182978 A JP 12182978A JP S5499555 A JPS5499555 A JP S5499555A
Authority
JP
Japan
Prior art keywords
inverse
features
level
phi2
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12182978A
Other languages
Japanese (ja)
Inventor
Shigeki Matsue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12182978A priority Critical patent/JPS5499555A/en
Publication of JPS5499555A publication Critical patent/JPS5499555A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Abstract

PURPOSE:To decrease the power consumption at the non-active time by providing the 1st and 2nd inverse circuits constituted by FET and then connecting the capacity between the gate and the source of the load FET in the 2nd inverse circuit. CONSTITUTION:The 1st inverse circuit consisting of FETQ11 and Q12 is provided along with the 2nd inverse circuit comprising FETQ21 and Q22, and capacitor C22 is connected between the gate and the source of load FETQ22 in the 2nd inverse circuit. When timing pulse phi is at a low level, output phi1 features a high level and phi2 features a low level respectively. Thus, no power is consumed by the two inverse circuits. When timing features a high level exceeding the level which is lower than power source VDD by threshold voltage VTH, phi2 features a low level with FETQ21 turned off. And FETQ23 is turned off since its gate is connected to the power source, and the charge at point B does not go away, thus obtaining the function of a high-efficiency bootstrap circuit. Thus, phi2 is turned to a high level. When phi is lowered, the level of point B can be lowered down suddenly through FETQ23. Thus, the power consumption can be decreased.
JP12182978A 1978-10-02 1978-10-02 Transistor circuit Pending JPS5499555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12182978A JPS5499555A (en) 1978-10-02 1978-10-02 Transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12182978A JPS5499555A (en) 1978-10-02 1978-10-02 Transistor circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9596672A Division JPS532308B2 (en) 1972-09-25 1972-09-25

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP57192137A Division JPS5890828A (en) 1982-11-01 1982-11-01 Transistor circuit

Publications (1)

Publication Number Publication Date
JPS5499555A true JPS5499555A (en) 1979-08-06

Family

ID=14820951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12182978A Pending JPS5499555A (en) 1978-10-02 1978-10-02 Transistor circuit

Country Status (1)

Country Link
JP (1) JPS5499555A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812348A (en) * 1981-07-15 1983-01-24 Nec Corp Semiconductor circuit
JP2012065042A (en) * 2010-09-14 2012-03-29 Fujitsu Semiconductor Ltd Logic circuit and memory using the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN=1971 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812348A (en) * 1981-07-15 1983-01-24 Nec Corp Semiconductor circuit
JPH0255974B2 (en) * 1981-07-15 1990-11-28 Nippon Electric Co
JP2012065042A (en) * 2010-09-14 2012-03-29 Fujitsu Semiconductor Ltd Logic circuit and memory using the same

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