JPS56100514A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS56100514A
JPS56100514A JP397980A JP397980A JPS56100514A JP S56100514 A JPS56100514 A JP S56100514A JP 397980 A JP397980 A JP 397980A JP 397980 A JP397980 A JP 397980A JP S56100514 A JPS56100514 A JP S56100514A
Authority
JP
Japan
Prior art keywords
inverter
connection point
stage
constituting
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP397980A
Other languages
Japanese (ja)
Other versions
JPS6134690B2 (en
Inventor
Ryuichi Sase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP397980A priority Critical patent/JPS56100514A/en
Publication of JPS56100514A publication Critical patent/JPS56100514A/en
Publication of JPS6134690B2 publication Critical patent/JPS6134690B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To make the charging speed to the electrostatic capacity slow to prevent a through current, by providing an electric resistance at the connection point between the drain and the source of complementary FETs constituting the inverter of the first stage. CONSTITUTION:Electric resistance 17 is provided at the connection point between the drain and the source of complementary FETs 5 and 6 constituting the inverter of the first stage. Then, the charging speed to electrostatic capacities 9 and 13 connected between high power source 3 and connection point 10 between the inverter of the first stage and the inverter of the next stage and between low power source 7 and connection point 14 between these inverters respectively becomes slow. Consequently, in respect to complementary FETs 11 and 15 constituting the inverter of the next stage, corresponding FETs 11 and 15 are not turned on simultaneously until the output voltage is changed. Therefore, a large through current is not generated, and power consumption is reduced.
JP397980A 1980-01-16 1980-01-16 Delay circuit Granted JPS56100514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP397980A JPS56100514A (en) 1980-01-16 1980-01-16 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP397980A JPS56100514A (en) 1980-01-16 1980-01-16 Delay circuit

Publications (2)

Publication Number Publication Date
JPS56100514A true JPS56100514A (en) 1981-08-12
JPS6134690B2 JPS6134690B2 (en) 1986-08-08

Family

ID=11572157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP397980A Granted JPS56100514A (en) 1980-01-16 1980-01-16 Delay circuit

Country Status (1)

Country Link
JP (1) JPS56100514A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224324A (en) * 1984-04-23 1985-11-08 Nec Corp Output buffer circuit
JPS61170129A (en) * 1985-01-24 1986-07-31 Seikosha Co Ltd Through-current preventing circuit of output inverter
EP0251910A2 (en) * 1986-06-25 1988-01-07 Fujitsu Limited CMOS output buffer circuit
EP0416409A2 (en) * 1989-09-06 1991-03-13 National Semiconductor Corporation Spike current reduction in CMOS switch drivers
FR2844404A1 (en) * 2002-06-13 2004-03-12 Hewlett Packard Co CONTROL CIRCUIT CONNECTED TO PULSE SHAPING CIRCUITS AND ITS OPERATING METHOD
JP2008005367A (en) * 2006-06-26 2008-01-10 Nec Electronics Corp Delay circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224324A (en) * 1984-04-23 1985-11-08 Nec Corp Output buffer circuit
JPS61170129A (en) * 1985-01-24 1986-07-31 Seikosha Co Ltd Through-current preventing circuit of output inverter
JPH0351334B2 (en) * 1985-01-24 1991-08-06 Seikosha Kk
EP0251910A2 (en) * 1986-06-25 1988-01-07 Fujitsu Limited CMOS output buffer circuit
EP0416409A2 (en) * 1989-09-06 1991-03-13 National Semiconductor Corporation Spike current reduction in CMOS switch drivers
FR2844404A1 (en) * 2002-06-13 2004-03-12 Hewlett Packard Co CONTROL CIRCUIT CONNECTED TO PULSE SHAPING CIRCUITS AND ITS OPERATING METHOD
US7239185B2 (en) 2002-06-13 2007-07-03 Hewlett-Packard Development Company, L.P. Driver circuit connected to pulse shaping circuitry
JP2008005367A (en) * 2006-06-26 2008-01-10 Nec Electronics Corp Delay circuit

Also Published As

Publication number Publication date
JPS6134690B2 (en) 1986-08-08

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