JPS57145437A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS57145437A
JPS57145437A JP56031694A JP3169481A JPS57145437A JP S57145437 A JPS57145437 A JP S57145437A JP 56031694 A JP56031694 A JP 56031694A JP 3169481 A JP3169481 A JP 3169481A JP S57145437 A JPS57145437 A JP S57145437A
Authority
JP
Japan
Prior art keywords
threshold voltage
circuit
inverter
type
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56031694A
Other languages
Japanese (ja)
Inventor
Koichiro Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56031694A priority Critical patent/JPS57145437A/en
Publication of JPS57145437A publication Critical patent/JPS57145437A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To obtain an input circuit having the reduced variance of the threshold voltage, by obtaining a voltage-dividing output from a point of series connection of plural enhancement type IGFETs which are connected in series. CONSTITUTION:An enhancement (E) type IGFETE11 with its drain 11 and gate 12 connected to an input terminal is grounded via EFETs E12-E16. The point of connection between EFETs E11-E15 forming the 1st diode circuit and the EFETE16 forming the 2nd diode circuit is connected to an inverter consisting of depletion (D) type IGFETD11 and an EFETE17. The sum of the threshold voltage of the 1st and 2nd diode circuits is set larger than the power supply voltage VCC of the inverter, and at the same time the threshold voltage of the 2nd diode circuit is set smaller than the threshold voltage of the inverter. As a result, the change of the circuit threshold voltage due to the variation of the IGFET element can be reduced.
JP56031694A 1981-03-05 1981-03-05 Input circuit Pending JPS57145437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56031694A JPS57145437A (en) 1981-03-05 1981-03-05 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56031694A JPS57145437A (en) 1981-03-05 1981-03-05 Input circuit

Publications (1)

Publication Number Publication Date
JPS57145437A true JPS57145437A (en) 1982-09-08

Family

ID=12338178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56031694A Pending JPS57145437A (en) 1981-03-05 1981-03-05 Input circuit

Country Status (1)

Country Link
JP (1) JPS57145437A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112427A (en) * 1984-11-06 1986-05-30 Nec Corp Logic circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110536A (en) * 1974-02-08 1975-08-30

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110536A (en) * 1974-02-08 1975-08-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112427A (en) * 1984-11-06 1986-05-30 Nec Corp Logic circuit

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