JPS56140726A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPS56140726A
JPS56140726A JP4301280A JP4301280A JPS56140726A JP S56140726 A JPS56140726 A JP S56140726A JP 4301280 A JP4301280 A JP 4301280A JP 4301280 A JP4301280 A JP 4301280A JP S56140726 A JPS56140726 A JP S56140726A
Authority
JP
Japan
Prior art keywords
transistor
turned
type
channel
input vin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4301280A
Other languages
Japanese (ja)
Inventor
Kanichi Miyazawa
Kazuhide Aoki
Shoji Shindo
Hiroyuki Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4301280A priority Critical patent/JPS56140726A/en
Publication of JPS56140726A publication Critical patent/JPS56140726A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To enable to form a system that includes various kinds of integrated circuits such as TTL, CMOS and single-channel MOS by using a depression-type MOS element for one side of a single-channel MOS type output circuit. CONSTITUTION:When the input Vin is at one level, the enhancement-type MOS transistor T6 of N channel type is turned on. At the same time, the depression-type MOS transistor T5 of N channel type is turned on faintly since the signal obtained by inverting the input Vin via an inverter 15 is supplied to the gate of the transistor T5. Thus the O-level value is obtained at the output Vout. On the other hand, the transistor T6 is turned off when the input Vin is at zero level. At the same time, the gate voltage of the transistor T5 is 1 and accordingly the transistor T5 is turned on strongly. As a result, the value up to the power supply voltage VDD can be fully obtained for the output Vout.
JP4301280A 1980-04-02 1980-04-02 Output circuit Pending JPS56140726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4301280A JPS56140726A (en) 1980-04-02 1980-04-02 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4301280A JPS56140726A (en) 1980-04-02 1980-04-02 Output circuit

Publications (1)

Publication Number Publication Date
JPS56140726A true JPS56140726A (en) 1981-11-04

Family

ID=12652065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4301280A Pending JPS56140726A (en) 1980-04-02 1980-04-02 Output circuit

Country Status (1)

Country Link
JP (1) JPS56140726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169359A (en) * 1985-10-17 1987-07-25 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Cmos input buffer circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5056142A (en) * 1973-09-13 1975-05-16
JPS53102660A (en) * 1977-02-21 1978-09-07 Hitachi Ltd Push pull buffer circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5056142A (en) * 1973-09-13 1975-05-16
JPS53102660A (en) * 1977-02-21 1978-09-07 Hitachi Ltd Push pull buffer circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169359A (en) * 1985-10-17 1987-07-25 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Cmos input buffer circuit

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