JPS56120209A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS56120209A
JPS56120209A JP2372180A JP2372180A JPS56120209A JP S56120209 A JPS56120209 A JP S56120209A JP 2372180 A JP2372180 A JP 2372180A JP 2372180 A JP2372180 A JP 2372180A JP S56120209 A JPS56120209 A JP S56120209A
Authority
JP
Japan
Prior art keywords
terminal
level
delay
depletion type
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2372180A
Other languages
Japanese (ja)
Inventor
Yasutaka Nagae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2372180A priority Critical patent/JPS56120209A/en
Publication of JPS56120209A publication Critical patent/JPS56120209A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks

Landscapes

  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To obtain the value of greater delay without increasing occupied area, by connecting depletion type MISFET grounded for the gate, between one input terminal and another output terminal of two stages of inverters. CONSTITUTION:Between the output terminal A of the 1st stage inverter consisting of a depletion type load MISFETTR1 and enhancement type driving MISFETTER2 and the input terminal B of the 2nd stage inverter consisting similar two MISFETs TR3, TR4, a depletion type MISFETTR5 in which one of the source or drain is connected to the terminal A and another is connected to the terminal B and the gate is grounded, is connected. Further, when the potential level of the input terminal In changes from high to low level, the level at the output terminal Out is at a low level with a delay, but when changes to high level, no delay is given.
JP2372180A 1980-02-27 1980-02-27 Delay circuit Pending JPS56120209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2372180A JPS56120209A (en) 1980-02-27 1980-02-27 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2372180A JPS56120209A (en) 1980-02-27 1980-02-27 Delay circuit

Publications (1)

Publication Number Publication Date
JPS56120209A true JPS56120209A (en) 1981-09-21

Family

ID=12118187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2372180A Pending JPS56120209A (en) 1980-02-27 1980-02-27 Delay circuit

Country Status (1)

Country Link
JP (1) JPS56120209A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4322379Y1 (en) * 1965-10-08 1968-09-19
JPS51123048A (en) * 1975-04-21 1976-10-27 Hitachi Ltd Delay circuit having the transfer gate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4322379Y1 (en) * 1965-10-08 1968-09-19
JPS51123048A (en) * 1975-04-21 1976-10-27 Hitachi Ltd Delay circuit having the transfer gate

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