JPH0186309U - - Google Patents
Info
- Publication number
- JPH0186309U JPH0186309U JP18163687U JP18163687U JPH0186309U JP H0186309 U JPH0186309 U JP H0186309U JP 18163687 U JP18163687 U JP 18163687U JP 18163687 U JP18163687 U JP 18163687U JP H0186309 U JPH0186309 U JP H0186309U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- drain
- inverting input
- input terminal
- predetermined reference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 238000000926 separation method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案に係るカレントミラー回路の第
１の実施例を示す回路図、第２図はこの第１の実
施例の具体的な回路構成例を示す回路図、第３図
は本考案の第２の実施例を示す回路図、第４図は
本考案の第３の実施例を示す回路図、第５図は本
考案の第４の実施例を示す回路図、第６図は本考
案の第５の実施例を示す回路図、第７図は従来の
同期分離回路を示す回路図、第８図は第７図の回
路の動作を説明するための特性図である。
１１，１２……Ｐ型ＭＯＳトランジスタ、１３
……Ｎ型ＭＯＳトランジスタ、１５……負荷、２
０……差動増幅器、２５……反転入力端子。
Fig. 1 is a circuit diagram showing a first embodiment of the current mirror circuit according to the present invention, Fig. 2 is a circuit diagram showing a specific example of the circuit configuration of this first embodiment, and Fig. 3 is a circuit diagram showing a specific example of the circuit configuration of the first embodiment. FIG. 4 is a circuit diagram showing a third embodiment of the present invention, FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention, and FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. FIG. 7 is a circuit diagram showing a conventional synchronous separation circuit, and FIG. 8 is a characteristic diagram for explaining the operation of the circuit shown in FIG. 7. 11, 12...P-type MOS transistor, 13
...N-type MOS transistor, 15 ...Load, 2
0... Differential amplifier, 25... Inverting input terminal.
Claims (1)
れた第１、第２のトランジスタと、 上記第１のトランジスタのドレインあるいはコ
レクタが非反転入力端子に接続され、所定の基準
電位が反転入力端子に供給され、出力端子が上記
共通接続されたゲートあるいはベースに接続され
た差動増幅器とを具備し、 上記第１のトランジスタのドレインあるいはコ
レクタ電位を上記所定の基準電位に等しくするこ
とを特徴とするカレントミラー回路。[Claims for Utility Model Registration] First and second transistors whose respective gates or bases are connected in common; the drain or collector of the first transistor is connected to a non-inverting input terminal; and a predetermined reference potential is connected to the first transistor. a differential amplifier having an inverting input terminal and an output terminal connected to the commonly connected gate or base, and making the drain or collector potential of the first transistor equal to the predetermined reference potential. A current mirror circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18163687U JPH0186309U (en) | 1987-11-28 | 1987-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18163687U JPH0186309U (en) | 1987-11-28 | 1987-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0186309U true JPH0186309U (en) | 1989-06-07 |
Family
ID=31473115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18163687U Pending JPH0186309U (en) | 1987-11-28 | 1987-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0186309U (en) |
-
1987
- 1987-11-28 JP JP18163687U patent/JPH0186309U/ja active Pending
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