JPH044431U

JPH044431U -

Info

Publication number: JPH044431U
Application number: JP4614490U
Authority: JP
Priority date: 1990-04-26
Filing date: 1990-04-26
Publication date: 1992-01-16

Description

[Brief explanation of the drawing]

第１図ａはこの考案の一実施例の半導体集積回
路の回路図、第１図ｂは第１図の半導体集積回路
の電圧波形図、第２図は第２の実施例の回路図、
第３図ａは従来の半導体集積回路の回路図、第３
図ｂは従来の半導体集積回路の電圧波形図である
。Ｍ１，Ｍ４……Ｐ型ＭＯＳトランジスタ、Ｍ２
，Ｍ３……Ｎ型ＭＯＳトランジスタ、ＩＮ……入
力端子、ＯＵＴ１，ＯＵＴ２……出力端子。 FIG. 1a is a circuit diagram of a semiconductor integrated circuit according to an embodiment of this invention, FIG. 1b is a voltage waveform diagram of the semiconductor integrated circuit of FIG. 1, and FIG. 2 is a circuit diagram of a second embodiment.
Figure 3a is a circuit diagram of a conventional semiconductor integrated circuit;
FIG. b is a voltage waveform diagram of a conventional semiconductor integrated circuit. M1, M4...P-type MOS transistor, M2
, M3...N-type MOS transistor, IN...input terminal, OUT1, OUT2...output terminal.

Claims

[Scope of utility model registration request]

There is an M
A semiconductor integrated circuit characterized in that an OS transistor is arranged, the gate of the MOS transistor is used as an input terminal, and the source and drain are used as output terminals, thereby outputting two symmetrical waveforms.