JPS63177054U - - Google Patents
Info
- Publication number
- JPS63177054U JPS63177054U JP1987066305U JP6630587U JPS63177054U JP S63177054 U JPS63177054 U JP S63177054U JP 1987066305 U JP1987066305 U JP 1987066305U JP 6630587 U JP6630587 U JP 6630587U JP S63177054 U JPS63177054 U JP S63177054U
- Authority
- JP
- Japan
- Prior art keywords
- delay element
- constituted
- semiconductor integrated
- type transistor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 230000000295 complement effect Effects 0.000 claims 1
- 230000005669 field effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例構成図、第２図はＰ
型ＭＯＳトランジスタの遅延素子の動作説明図、
第３図はＮ型ＭＯＳトランジスタの遅延素子の動
作説明図、第４図は従来の論理ゲート・アレイの
構成図、第５図は従来の遅延素子形成手法説明図
である。
１……ゲート、２……Ｐ型ＭＯＳトランジスタ
の基本ゲートセル領域、３……Ｎ型ＭＯＳトラン
ジスタの基本ゲートセル領域。
Figure 1 is a configuration diagram of one embodiment of the present invention, Figure 2 is a P
An explanatory diagram of the operation of a delay element of a type MOS transistor,
FIG. 3 is an explanatory diagram of the operation of a delay element of an N-type MOS transistor, FIG. 4 is a configuration diagram of a conventional logic gate array, and FIG. 5 is an explanatory diagram of a conventional method of forming a delay element. 1... Gate, 2... Basic gate cell region of P-type MOS transistor, 3... Basic gate cell region of N-type MOS transistor.
Claims (1)
成された基本ゲートセル中に、回路素子と遅延素
子を形成した半導体集積回路において、Ｎ型トラ
ンジスタにより構成した遅延素子とＰ型トランジ
スタにより構成した遅延素子を形成したことを特
徴とする遅延素子を含む半導体集積回路装置。 In a semiconductor integrated circuit in which a circuit element and a delay element are formed in a basic gate cell constituted by complementary MIS field effect transistors, a delay element constituted by an N-type transistor and a delay element constituted by a P-type transistor are formed. A semiconductor integrated circuit device including a delay element, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987066305U JPS63177054U (en) | 1987-05-01 | 1987-05-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987066305U JPS63177054U (en) | 1987-05-01 | 1987-05-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63177054U true JPS63177054U (en) | 1988-11-16 |
Family
ID=30904189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987066305U Pending JPS63177054U (en) | 1987-05-01 | 1987-05-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63177054U (en) |
-
1987
- 1987-05-01 JP JP1987066305U patent/JPS63177054U/ja active Pending
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