JPH01169049U - - Google Patents
Info
- Publication number
- JPH01169049U JPH01169049U JP6524788U JP6524788U JPH01169049U JP H01169049 U JPH01169049 U JP H01169049U JP 6524788 U JP6524788 U JP 6524788U JP 6524788 U JP6524788 U JP 6524788U JP H01169049 U JPH01169049 U JP H01169049U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- protection device
- power supply
- supply terminal
- semiconductor protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 1
Description
第１図は本考案による半導体保護装置を説明す
る断面図、第２図は第１図の等価回路図、第３図
および第４図は従来の半導体保護装置を説明する
回路図および断面図である。
１は半導体基板、２はＮウエル領域、３はＰチ
ヤンネルＭＯＳトランジスタ、４，５はソースド
レイン領域、６はゲート酸化膜、７はゲート電極
、８，９はコンタクト領域である。
FIG. 1 is a sectional view illustrating a semiconductor protection device according to the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIGS. 3 and 4 are a circuit diagram and sectional view illustrating a conventional semiconductor protection device. be. 1 is a semiconductor substrate, 2 is an N-well region, 3 is a P-channel MOS transistor, 4 and 5 are source/drain regions, 6 is a gate oxide film, 7 is a gate electrode, and 8 and 9 are contact regions.
Claims (1)
圧を有するＭＯＳトランジスタを設け、前記ＭＯ
Ｓトランジスタのゲートとドレインを電源端子に
接続し、ソースをアースに接続することを特徴と
する半導体保護装置。 (2) 前記ＭＯＳトランジスタをＮ型ウエル領域
内に形成したＰチヤンネルＭＯＳトランジスタで
構成することを特徴とする請求項１記載の半導体
保護装置。[Claims for Utility Model Registration] (1) A MOS transistor having a predetermined withstand voltage is provided at the input terminal of the power supply terminal to the internal circuit, and
A semiconductor protection device characterized in that the gate and drain of an S transistor are connected to a power supply terminal, and the source is connected to ground. (2) The semiconductor protection device according to claim 1, wherein the MOS transistor is a P-channel MOS transistor formed in an N-type well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6524788U JPH01169049U (en) | 1988-05-18 | 1988-05-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6524788U JPH01169049U (en) | 1988-05-18 | 1988-05-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01169049U true JPH01169049U (en) | 1989-11-29 |
Family
ID=31290686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6524788U Pending JPH01169049U (en) | 1988-05-18 | 1988-05-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01169049U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209694A (en) * | 1990-01-12 | 1991-09-12 | Sharp Corp | Semiconductor memory device |
| JPH0398254U (en) * | 1990-01-24 | 1991-10-11 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60231355A (en) * | 1984-04-27 | 1985-11-16 | Mitsubishi Electric Corp | Complementary type semiconductor integrated circuit |
-
1988
- 1988-05-18 JP JP6524788U patent/JPH01169049U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60231355A (en) * | 1984-04-27 | 1985-11-16 | Mitsubishi Electric Corp | Complementary type semiconductor integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209694A (en) * | 1990-01-12 | 1991-09-12 | Sharp Corp | Semiconductor memory device |
| JPH0398254U (en) * | 1990-01-24 | 1991-10-11 |