JPH0352U - - Google Patents
Info
- Publication number
- JPH0352U JPH0352U JP5777989U JP5777989U JPH0352U JP H0352 U JPH0352 U JP H0352U JP 5777989 U JP5777989 U JP 5777989U JP 5777989 U JP5777989 U JP 5777989U JP H0352 U JPH0352 U JP H0352U
- Authority
- JP
- Japan
- Prior art keywords
- input
- fet
- nmos
- terminal
- internal circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の半導体集積装置の入力保護回
路の一実施例の回路図、第２図は第１図のＮＭＯ
Ｓ・ＦＥＴの断面図、第３図は従来の半導体集積
装置の入力保護回路の一例の回路図、第４図は第
３図の入力保護回路を使用した場合の問題点を説
明するための回路図、第５図は第３図の抵抗の断
面図である。
１２：ＮＭＯＳ・ＦＥＴ、１３：ダイオード、
Ｉ：信号入力端子、ＶＤ：電源端子、ＶＳ：接地
端子。
FIG. 1 is a circuit diagram of an embodiment of the input protection circuit of the semiconductor integrated device of the present invention, and FIG.
A cross-sectional view of an S-FET, FIG. 3 is a circuit diagram of an example of an input protection circuit of a conventional semiconductor integrated device, and FIG. 4 is a circuit for explaining problems when using the input protection circuit of FIG. 3. 5 is a sectional view of the resistor shown in FIG. 3. 12: NMOS/FET, 13: Diode,
I: Signal input terminal, VD: Power supply terminal, VS: Ground terminal.
Claims (1)
ダイオードとからなり、 前記ＮＭＯＳ・ＦＥＴのソースは信号入力端子
に、そのドレインは内部回路入力に、そのゲート
は電源端子に接続され、 前記ダイオードは、そのアノードは前記内部回
路入力に、そのカソードは接地端子に接続される
ことを特徴とする半導体集積装置の入力保護回路
。[Claims for Utility Model Registration] Consisting of an NMOS/FET and a diode formed on a semiconductor substrate, the source of the NMOS/FET is connected to a signal input terminal, its drain is connected to an internal circuit input, and its gate is connected to a power supply terminal. An input protection circuit for a semiconductor integrated device, wherein the diode has an anode connected to the internal circuit input and a cathode connected to a ground terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5777989U JPH0352U (en) | 1989-05-19 | 1989-05-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5777989U JPH0352U (en) | 1989-05-19 | 1989-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0352U true JPH0352U (en) | 1991-01-07 |
Family
ID=31582797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5777989U Pending JPH0352U (en) | 1989-05-19 | 1989-05-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0352U (en) |
-
1989
- 1989-05-19 JP JP5777989U patent/JPH0352U/ja active Pending