JPH02145818U - - Google Patents
Info
- Publication number
- JPH02145818U JPH02145818U JP5622189U JP5622189U JPH02145818U JP H02145818 U JPH02145818 U JP H02145818U JP 5622189 U JP5622189 U JP 5622189U JP 5622189 U JP5622189 U JP 5622189U JP H02145818 U JPH02145818 U JP H02145818U
- Authority
- JP
- Japan
- Prior art keywords
- output terminal
- region
- semiconductor
- prevention circuit
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Description
第１図ａは本考案の実施例を示す断面図、第１
図ｂは第１図ａに示された構造の回路図、第２図
ａは本考案の他の実施例を示す断面図、第２図ｂ
は第２図ａに示された構造の回路図である。
１，１２……半導体基板、２，１３……ソース
、３，１４……ドレイン、４，１５……ゲート、
５……Ｎ−ｗｅｌｌ、１６……Ｐ−ｗｅｌｌ、８
，１９……出力端子、９，２０……出力ＭＯＳト
ランジスタ、１０……ＰＮＰトランジスタ、２１
……ＮＰＮトランジスタ、１１，２２……接合容
量。
Figure 1a is a sectional view showing an embodiment of the present invention;
Figure b is a circuit diagram of the structure shown in Figure 1a, Figure 2a is a sectional view showing another embodiment of the present invention, Figure 2b
2a is a circuit diagram of the structure shown in FIG. 2a. 1, 12... Semiconductor substrate, 2, 13... Source, 3, 14... Drain, 4, 15... Gate,
5...N-well, 16...P-well, 8
, 19... Output terminal, 9, 20... Output MOS transistor, 10... PNP transistor, 21
...NPN transistor, 11, 22... Junction capacitance.
Claims (1)
たＭＯＳトランジスタを備えた集積回路の静電破
壊防止回路に於いて、 半導体基板中に形成された一導電型の半導体層
と、 該半導体層中に形成された逆導電型の第１及び
第２領域と、 を備え、 前記第１領域を前記出力端子に接続すると共に
前記第２領域を所定の電源に接続したことを特徴
とする静電破壊防止回路。[Claims for Utility Model Registration] In an electrostatic breakdown prevention circuit for an integrated circuit comprising an output terminal and a MOS transistor whose drain is connected to the output terminal, a semiconductor of one conductivity type formed in a semiconductor substrate. a layer, and first and second regions of opposite conductivity types formed in the semiconductor layer, the first region being connected to the output terminal and the second region being connected to a predetermined power source. Electrostatic damage prevention circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989056221U JPH0753307Y2 (en) | 1989-05-16 | 1989-05-16 | ESD protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989056221U JPH0753307Y2 (en) | 1989-05-16 | 1989-05-16 | ESD protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02145818U true JPH02145818U (en) | 1990-12-11 |
| JPH0753307Y2 JPH0753307Y2 (en) | 1995-12-06 |
Family
ID=31579854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989056221U Expired - Lifetime JPH0753307Y2 (en) | 1989-05-16 | 1989-05-16 | ESD protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0753307Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63146460A (en) * | 1986-12-10 | 1988-06-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1989
- 1989-05-16 JP JP1989056221U patent/JPH0753307Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63146460A (en) * | 1986-12-10 | 1988-06-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0753307Y2 (en) | 1995-12-06 |
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