JPS62166650U - - Google Patents
Info
- Publication number
- JPS62166650U JPS62166650U JP5551086U JP5551086U JPS62166650U JP S62166650 U JPS62166650 U JP S62166650U JP 5551086 U JP5551086 U JP 5551086U JP 5551086 U JP5551086 U JP 5551086U JP S62166650 U JPS62166650 U JP S62166650U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- well region
- semiconductor device
- semiconductor substrate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案にＣＭＯＳ半導体装置を説明す
る断面図、第２図は本考案のラツチアツプ現象を
説明する等価回路図、第３図は本考案に用いるモ
アマイナス電位発生回路を説明する回路図、第４
図は従来のＣＭＯＳ半導体装置を説明する上面図
、第５図は従来のラツチアツプの動作を説明する
断面図である。
１は半導体基板、５はＰチヤンネルＭＯＳトラ
ンジスタ、６はウエル領域、１０はＮチヤンネル
ＭＯＳトランジスタ、１１はＮ＋型コンタクト領
域、１３は寄生ＰＮＰトランジスタ、１４は寄生
ＮＰＮトランジスタである。
FIG. 1 is a cross-sectional view illustrating a CMOS semiconductor device according to the present invention, FIG. 2 is an equivalent circuit diagram illustrating the latch-up phenomenon of the present invention, and FIG. 3 is a circuit diagram illustrating a more minus potential generation circuit used in the present invention. , 4th
The figure is a top view illustrating a conventional CMOS semiconductor device, and FIG. 5 is a sectional view illustrating the operation of a conventional latchup. 1 is a semiconductor substrate, 5 is a P-channel MOS transistor, 6 is a well region, 10 is an N-channel MOS transistor, 11 is an N + type contact region, 13 is a parasitic PNP transistor, and 14 is a parasitic NPN transistor.
Claims (1)
と前記半導体基板表面に形成した一導電チヤンネ
ルのＭＯＳトランジスタと前記ウエル領域に形成
した逆導電チヤンネルのＭＯＳトランジスタとを
具備するＣＭＯＳ半導体装置において、前記逆導
電チヤンネルのＭＯＳトランジスタのソース領域
を接地し、前記ウエル領域を接地電位以下の電圧
を印加することを特徴とするＣＭＯＳ半導体装置
。 A CMOS semiconductor device comprising a semiconductor substrate of one conductivity type, a well region of the opposite conductivity type, a MOS transistor of one conductivity channel formed on the surface of the semiconductor substrate, and a MOS transistor of the opposite conductivity channel formed in the well region, 1. A CMOS semiconductor device, wherein a source region of a MOS transistor in a reverse conduction channel is grounded, and a voltage lower than a ground potential is applied to the well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5551086U JPS62166650U (en) | 1986-04-14 | 1986-04-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5551086U JPS62166650U (en) | 1986-04-14 | 1986-04-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62166650U true JPS62166650U (en) | 1987-10-22 |
Family
ID=30883467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5551086U Pending JPS62166650U (en) | 1986-04-14 | 1986-04-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62166650U (en) |
-
1986
- 1986-04-14 JP JP5551086U patent/JPS62166650U/ja active Pending
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