JPS63147839U - - Google Patents
Info
- Publication number
- JPS63147839U JPS63147839U JP4021887U JP4021887U JPS63147839U JP S63147839 U JPS63147839 U JP S63147839U JP 4021887 U JP4021887 U JP 4021887U JP 4021887 U JP4021887 U JP 4021887U JP S63147839 U JPS63147839 U JP S63147839U
- Authority
- JP
- Japan
- Prior art keywords
- well region
- vss power
- mos transistor
- power supply
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 description 2
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案によるＣＭＯＳ半導体装置を説
明する上面図、第２図は本考案のラツチアツプ現
象を説明する断面図、第３図は本考案の他の実施
例を説明する上面図、第４図は従来のＣＭＯＳ半
導体装置を説明する上面図、第５図は従来のラツ
チアツプ現象を説明する断面図である。
１はＮ型半導体基板、５はＰチヤンネルＭＯＳ
トランジスタ、６はＰ型ウエル領域、１０はＮチ
ヤンネルＭＯＳトランジスタ、１２はＶＤＤ電源
ライン、１３はＶＳＳ電源ライン、１４はバイア
スコンタクト領域、１５は寄生ＰＮＰトランジス
タ、１６は寄生ＮＰＮトランジスタである。
FIG. 1 is a top view illustrating a CMOS semiconductor device according to the present invention, FIG. 2 is a sectional view illustrating the latch-up phenomenon of the present invention, FIG. 3 is a top view illustrating another embodiment of the present invention, and FIG. The figure is a top view illustrating a conventional CMOS semiconductor device, and FIG. 5 is a sectional view illustrating a conventional latch-up phenomenon. 1 is an N-type semiconductor substrate, 5 is a P-channel MOS
The transistors include a P-type well region 6, an N-channel MOS transistor 10, a VDD power line 12, a VSS power line 13, a bias contact region 14, a parasitic PNP transistor 15, and a parasitic NPN transistor 16.
Claims (1)
と前記半導体基板表面に形成した一導電チヤンネ
ルのＭＯＳトランジスタと前記ウエル領域に形成
した逆導電チヤンネルのＭＯＳトランジスタと前
記基板表面の絶縁膜上を延在されるＶＤＤ電源ラ
インおよびＶＳＳ電源ラインとを具備するＣＭＯ
Ｓ半導体装置において、前記ＶＳＳ電源ラインと
交わる前記ウエル領域の端部近傍に前記ＶＳＳ電
源ラインに接続したバイアスコンタクト領域を形
成することを特徴とするＣＭＯＳ半導体装置。 A semiconductor substrate of one conductivity type, a well region of the opposite conductivity type, a MOS transistor of one conductivity channel formed on the surface of the semiconductor substrate, a MOS transistor of the opposite conductivity channel formed in the well region, and an insulating film on the surface of the substrate. A CMO equipped with a VDD power line and a VSS power line
A CMOS semiconductor device characterized in that a bias contact region connected to the VSS power supply line is formed near an end of the well region that intersects with the VSS power supply line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4021887U JPS63147839U (en) | 1987-03-19 | 1987-03-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4021887U JPS63147839U (en) | 1987-03-19 | 1987-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63147839U true JPS63147839U (en) | 1988-09-29 |
Family
ID=30854110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4021887U Pending JPS63147839U (en) | 1987-03-19 | 1987-03-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63147839U (en) |
-
1987
- 1987-03-19 JP JP4021887U patent/JPS63147839U/ja active Pending
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