JPS61106049U - - Google Patents
Info
- Publication number
- JPS61106049U JPS61106049U JP19160084U JP19160084U JPS61106049U JP S61106049 U JPS61106049 U JP S61106049U JP 19160084 U JP19160084 U JP 19160084U JP 19160084 U JP19160084 U JP 19160084U JP S61106049 U JPS61106049 U JP S61106049U
- Authority
- JP
- Japan
- Prior art keywords
- region
- mos transistor
- conductivity type
- semiconductor substrate
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案によるＣ―ＭＯＳトランジスタ
を示す断面図、第２図は従来のＣ―ＭＯＳトラン
ジスタを示す断面図、第３図はＣ―ＭＯＳトラン
ジスタのラツチアツプ現象を説明する等価回路図
である。
主な図番の説明、１は半導体基板、２はＰ＋型
ウエル領域、３はＰ型ウエル領域、１０は絶縁酸
化膜である。
Fig. 1 is a cross-sectional view showing a C-MOS transistor according to the present invention, Fig. 2 is a cross-sectional view showing a conventional C-MOS transistor, and Fig. 3 is an equivalent circuit diagram explaining the latch-up phenomenon of a C-MOS transistor. . Explanation of main figure numbers: 1 is a semiconductor substrate, 2 is a P + type well region, 3 is a P type well region, and 10 is an insulating oxide film.
Claims (1)
れた逆導電型のウエル領域と該逆導電型ウエル領
域内に設けられた一導電チヤンネルのＭＯＳトラ
ンジスタを構成するソース領域、ドレイン領域及
びコンタクト領域と前記半導体基板に設けられた
逆導電チヤンネルＭＯＳトランジスタを構成する
ソース領域、ドレイン領域及びコンタクト領域と
を具備した相補型ＭＯＳトランジスタにおいて、
前記逆導電型ウエル領域が基板と接触する部分に
設けられた高濃度の第１領域と該第１領域内に設
けられた前記第１領域よりは低濃度の第２領域と
からなることを特徴とする相補型ＭＯＳトランジ
スタ。 A semiconductor substrate of one conductivity type, a well region of an opposite conductivity type provided on the semiconductor substrate, and a source region, a drain region, and a contact region constituting a MOS transistor of one conductivity channel provided in the well region of the opposite conductivity type. A complementary MOS transistor comprising a source region, a drain region, and a contact region constituting a reverse conduction channel MOS transistor provided on the semiconductor substrate,
The reverse conductivity type well region is characterized by comprising a first region with a high concentration provided in a portion in contact with the substrate and a second region with a lower concentration than the first region provided within the first region. Complementary MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19160084U JPS61106049U (en) | 1984-12-18 | 1984-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19160084U JPS61106049U (en) | 1984-12-18 | 1984-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61106049U true JPS61106049U (en) | 1986-07-05 |
Family
ID=30749039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19160084U Pending JPS61106049U (en) | 1984-12-18 | 1984-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61106049U (en) |
-
1984
- 1984-12-18 JP JP19160084U patent/JPS61106049U/ja active Pending
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