JPS624149U - - Google Patents
Info
- Publication number
- JPS624149U JPS624149U JP8875086U JP8875086U JPS624149U JP S624149 U JPS624149 U JP S624149U JP 8875086 U JP8875086 U JP 8875086U JP 8875086 U JP8875086 U JP 8875086U JP S624149 U JPS624149 U JP S624149U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- switching
- load
- junction capacitance
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims 1
- 239000011159 matrix material Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案に依る半導体記憶装置を説明す
る上面図、第２図は周知のＲＯＭを説明する等価
回路図である。
１は負荷ＩＧ ＦＥＴ、２はスイツチングＩＧ
ＦＥＴ、５はソースドレイン領域、６は本発明
の特徴とする拡散領域、７はＲＯＭの出力取り出
しのための拡散領域である。
FIG. 1 is a top view illustrating a semiconductor memory device according to the present invention, and FIG. 2 is an equivalent circuit diagram illustrating a well-known ROM. 1 is load IG FET, 2 is switching IG
FET, 5 is a source/drain region, 6 is a diffusion region which is a feature of the present invention, and 7 is a diffusion region for taking out the output of the ROM.
Claims (1)
ＩＧ ＦＥＴという。）に直列に接続される複数
のスイツチングＩＧ ＦＥＴで形成される行と前
記スイツチングＩＧ ＦＥＴのゲート電極として
働く複数の導電層の列で構成されるマトリツクス
状半導体記憶装置において、前記負荷ＩＧ ＦＥ
Ｔと前記スイツチングＩＧ ＦＥＴとの接続点に
ある前記負荷ＩＧ ＦＥＴのソースあるいはドレ
イン領域を前記行間に延在させて前記スイツチン
グＩＧ ＦＥＴの寄生容量より大きい接合容量を
形成し、前記接合容量の電荷で前記スイツチング
ＩＧ ＦＥＴの接合容量へ充電することを特徴と
半導体記憶装置。 It consists of a row formed by a plurality of switching IG FETs connected in series to a load insulated gate field effect transistor (hereinafter referred to as IG FET) and a column of a plurality of conductive layers serving as gate electrodes of the switching IG FETs. In the matrix semiconductor memory device, the load IG FE
The source or drain region of the load IG FET at the connection point between the load IG FET and the switching IG FET is extended between the rows to form a junction capacitance larger than the parasitic capacitance of the switching IG FET, and the charge of the junction capacitance is A semiconductor memory device characterized in that the junction capacitance of the switching IG FET is charged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8875086U JPH037964Y2 (en) | 1986-06-11 | 1986-06-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8875086U JPH037964Y2 (en) | 1986-06-11 | 1986-06-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS624149U true JPS624149U (en) | 1987-01-12 |
| JPH037964Y2 JPH037964Y2 (en) | 1991-02-27 |
Family
ID=30642189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8875086U Expired JPH037964Y2 (en) | 1986-06-11 | 1986-06-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH037964Y2 (en) |
-
1986
- 1986-06-11 JP JP8875086U patent/JPH037964Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH037964Y2 (en) | 1991-02-27 |
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