JPH0195763U - - Google Patents

Info

Publication number
JPH0195763U
JPH0195763U JP19141087U JP19141087U JPH0195763U JP H0195763 U JPH0195763 U JP H0195763U JP 19141087 U JP19141087 U JP 19141087U JP 19141087 U JP19141087 U JP 19141087U JP H0195763 U JPH0195763 U JP H0195763U
Authority
JP
Japan
Prior art keywords
wiring layer
resistance
semiconductor integrated
integrated circuit
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19141087U
Other languages
Japanese (ja)
Other versions
JP2519889Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987191410U priority Critical patent/JP2519889Y2/en
Publication of JPH0195763U publication Critical patent/JPH0195763U/ja
Application granted granted Critical
Publication of JP2519889Y2 publication Critical patent/JP2519889Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案のセンスアンプのレイアウト構
成図、第２図はセンスアンプの回路図、第３図は
従来のセンスアンプのレイアウト構成図である。 Ｐ１，Ｐ２……Ｐ型半導体層、Ｎ１，Ｎ２……
Ｎ型半導体層、ＰＭＯＳ１，ＰＭＯＳ２……Ｐチ
ヤネルＭＯＳトランジスタ、ＮＭＯＳ１，ＮＭＯ
Ｓ２……ＮチヤネルＭＯＳトランジスタ、Ｉ……
第１金属配線層、……第２金属配線層、……
高抵抗配線層（多結晶シリコン層）、Ｃ０１，Ｃ
０２，Ｃ１２，Ｃ１３，Ｃ２３……コンタクト。 FIG. 1 is a layout configuration diagram of a sense amplifier according to the present invention, FIG. 2 is a circuit diagram of the sense amplifier, and FIG. 3 is a layout configuration diagram of a conventional sense amplifier. P1, P2...P-type semiconductor layer, N1, N2...
N-type semiconductor layer, PMOS1, PMOS2...P channel MOS transistor, NMOS1, NMO
S2...N channel MOS transistor, I...
First metal wiring layer, ... second metal wiring layer, ...
High resistance wiring layer (polycrystalline silicon layer), C 01 , C
02 , C12 , C13 , C23 ...Contact.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ゲート電極を高抵抗配線層で形成した複数個の
素子を有し、かつ選択された素子のゲート電極を
相互に接続する回路を含む半導体集積回路装置に
おいて、前記高抵抗配線層を各素子領域及びコン
タクト領域のみに限定し、これら高抵抗配線層を
低抵抗又は低容量配線層で相互に接続したことを
特徴とする半導体集積回路装置。 In a semiconductor integrated circuit device having a plurality of elements each having a gate electrode formed of a high-resistance wiring layer, and including a circuit that interconnects the gate electrodes of selected elements, the high-resistance wiring layer is connected to each element region and A semiconductor integrated circuit device characterized in that these high-resistance wiring layers are connected to each other by a low-resistance or low-capacitance wiring layer only in a contact region.
JP1987191410U 1987-12-18 1987-12-18 Semiconductor integrated circuit device Expired - Lifetime JP2519889Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987191410U JP2519889Y2 (en) 1987-12-18 1987-12-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987191410U JP2519889Y2 (en) 1987-12-18 1987-12-18 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0195763U true JPH0195763U (en) 1989-06-26
JP2519889Y2 JP2519889Y2 (en) 1996-12-11

Family

ID=31482325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987191410U Expired - Lifetime JP2519889Y2 (en) 1987-12-18 1987-12-18 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2519889Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59129460A (en) * 1983-01-14 1984-07-25 Nec Corp Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59129460A (en) * 1983-01-14 1984-07-25 Nec Corp Semiconductor memory device

Also Published As

Publication number Publication date
JP2519889Y2 (en) 1996-12-11

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